37
Specification Update
AAN65.
Rapid Core C3/C6 Transitions May Cause Unpredictable System
Behavior
Problem:
Under a complex set of internal conditions, cores rapidly performing C3/C6 transitions
in a system with Intel
®
Hyper-Threading Technology enabled may cause a machine
check error (IA32_MCi_STATUS.MCACOD = 0x0106), system hang or unpredictable
system behavior.
Implication:
This erratum may cause a machine check error, system hang or unpredictable system
behavior.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAN66.
Performance Monitor Events INSTR_RETIRED and
MEM_INST_RETIRED May Count Inaccurately
Problem:
The performance monitor event INSTR_RETIRED (Event C0H) should count the number
of instructions retired, and MEM_INST_ RETIRED (Event 0BH) should count the number
of load or store instructions retired. However, due to this erratum, they may
undercount.
Implication:
The performance monitor event INSTR_RETIRED and MEM_INST_RETIRED may reflect
a count lower than the actual number of events.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAN67.
A Page Fault May Not be Generated When the PS bit is set to "1" in a
PML4E or PDPTE
Problem:
On processors supporting Intel
®
64 architecture, the PS bit (Page Size, bit 7) is
reserved in PML4Es and PDPTEs. If the translation of the linear address of a memory
access encounters a PML4E or a PDPTE with PS set to 1, a page fault should occur. Due
to this erratum, PS of such an entry is ignored and no page fault will occur due to its
being set.
Implication:
Software may not operate properly if it relies on the processor to deliver page faults
when reserved bits are set in paging-structure entries.
Workaround:
Software should not set bit 7 in any PML4E or PDPTE that has Present Bit (Bit 0) set to
"1".
Status:
For the steppings affected, see the Summary Tables of Changes.
AAN68.
CPURESET Bit Does Not Get Cleared
Problem:
CPURESET (bit 10 of SYRE Device 8; Function 2; Offset 0CCH) allows the processor to
be independently reset without assertion of the PLTRST# signal upon a 0 to 1
transition. The CPURESET bit does not get cleared and must be cleared by software.
Implication:
The processor will not be reset if a 1 is written to this bit while it is already a one.
Workaround:
The CPURESET bit must be cleared by software prior to setting it.
Status:
For the steppings affected, see the Summary Tables of Changes.
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