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Add-In Cards

Development Kit User’s Manual

Table 24. Board Rework to Support Display Port on Saddlestring

STUFF

UNSTUFF

BOM

Description

C6C11

CAPC,X5R,0402,10V,10%,0.1uF.
IPN : A36096-043

To disconnect TX11#
from MCH to PEG

C6C13

CAPC,X5R,0402,10V,10%,0.1uF.
IPN : A36096-044

To disconnect TX11 from
MCH to PEG

C6C15

CAPC,X5R,0402,10V,10%,0.1uF.
IPN : A36096-045

To disconnect TX10#
from MCH to PEG

C6C18

CAPC,X5R,0402,10V,10%,0.1uF.
IPN : A36096-046

To disconnect TX10 from
MCH to PEG

C6D2

CAPC,X5R,0402,10V,10%,0.1uF.
IPN : A36096-047

To disconnect TX9# from
MCH to PEG

C6D3

CAPC,X5R,0402,10V,10%,0.1uF.
IPN : A36096-048

To disconnect TX9 from
MCH to PEG

C6D7

CAPC,X5R,0402,10V,10%,0.1uF.
IPN : A36096-049

To disconnect TX7# from
MCH to PEG

C6D9

CAPC,X5R,0402,10V,10%,0.1uF.
IPN : A36096-050

To disconnect TX7 from
MCH to PEG

C6C10

CAPC,X5R,0402,10V,10%,0.1uF.
IPN : A36096-051

To route TX11 from
Docking connector to MCH

C6C12

CAPC,X5R,0402,10V,10%,0.1uF.
IPN : A36096-052

To route TX11# from
Docking connector to MCH

C6D6

CAPC,X5R,0402,10V,10%,0.1uF.
IPN : A36096-053

To route TX8 from
Docking connector to MCH

C6D8

CAPC,X5R,0402,10V,10%,0.1uF.
IPN : A36096-054

To route TX8# from
Docking connector to MCH

C6C16

CAPC,X5R,0402,10V,10%,0.1uF.
IPN : A36096-055

To route TX10 from
Docking connector to MCH

C6C17

CAPC,X5R,0402,10V,10%,0.1uF.
IPN : A36096-056

To route TX10# from
Docking connector to MCH

C6D1

CAPC,X5R,0402,10V,10%,0.1uF.
IPN : A36096-057

To route TX9 from
Docking connector to MCH

C6D4

CAPC,X5R,0402,10V,10%,0.1uF.
IPN : A36096-058

To route TX9# from
Docking connector to MCH

R6R1

RESD,0402,5%,1/16W,0
IPN : A93549-001

R6R2

RESD,0402,5%,1/16W,0
IPN : A93549-002

These are the AUX signals
of the Display Port. It
connects to MCH on RX9
and RX9# respectively

R6R3

RESD,0402,5%,1/16W,0
IPN : A93549-003

To connect the level
translated Hot Plug
Docking (HPD) to MCH

Содержание BX80580Q9400 - Core 2 Quad 2.66 GHz Processor

Страница 1: ...Document Number 320503 001 Intel CoreTM 2 Duo Processor and Intel GS45 Express Chipset with DDR3 System Memory Development Kit User s Manual September 2008...

Страница 2: ...flicts or incompatibilities arising from future changes to them Intel processor numbers are not a measure of performance Processor numbers differentiate features within each processor family not acros...

Страница 3: ...AC to DC Power Supply Mobile Power Mode 22 2 7 Power Down 23 2 8 System BIOS 23 2 8 1 Configuring the BIOS 23 2 8 2 Programming BIOS Using a Bootable USB Device 24 3 Development Board Features 26 3 1...

Страница 4: ...BSEL Jumper Settings 56 4 4 Power and Reset Push Buttons 56 4 5 Net Detect Button 57 4 6 LEDs 58 4 7 Other Headers 59 4 7 1 H8 Programming Headers 59 4 7 2 Sideband and Test Headers 60 Appendix A Add...

Страница 5: ...62 Figure 12 Eaglemont Add in Card 63 Figure 13 Location of Resistors for Rework before Rework 64 Figure 14 Location of Resistors for Rework after Rework 64 Figure 15 Location of Resistors for Rework...

Страница 6: ...ts mapping 38 Table 12 System Power Management States 41 Table 13 System Power Management M States 42 Table 14 Digital Multi Meter Comparison 43 Table 15 System Voltage Rails 43 Table 16 Development B...

Страница 7: ...Development Kit User s Manual 7 Revision History Document Number Revision Number Description Revision Date 320503 001 Public launch release Sept 2008...

Страница 8: ...Table 18 All other components and references are the same between boards For the latest information about the Intel CoreTM 2 Duo processor and Intel GS45 Express Chipset Development Kit visit http de...

Страница 9: ...processor heatsink 1 2 Text Conventions The notations listed in Table 1 may be used throughout this manual Table 1 Text Conventions Notation Definition The pound symbol appended to a signal name indic...

Страница 10: ...lize CMOS voltage levels on any signals that connect to the processor As a result legacy input signals such as A20M IGNNE INIT LINT0 INTR LINT1 NMI PWRGOOD SMI SLP and STPCLK utilize GTL input buffers...

Страница 11: ...s the microprocessor bus of the processor System Management Bus A two wire interface through which various system components may communicate VCC CPU core VCC CPU core is the core power for the process...

Страница 12: ...de EHCI Enhanced Host Controller Interface EMA Extended Media Access eSATA External SATA Serial ATA ESD Electrostatic Discharge FCBGA Flip Chip Ball Grid Array FCPGA Flip Chip Pin Grid Array FS Full s...

Страница 13: ...ini Ball Grid Array MEC Media Expansion Card MHz Mega Hertz MT s Mega Transfers per second NMI Non Maskable Interrupt OEM Original Equipment Manufacturer PEG PCI Express Graphics PCI Peripheral Connec...

Страница 14: ...sal Serial Bus VGA Video Graphics Adapter VID Voltage Identification WiMAX Wireless Communications Standard WLAN Wireless Local Area Network VREG or VR Voltage Regulator WWAN Wireless Wide Area Networ...

Страница 15: ...tor SFF Platform Design Guide Contact your Intel representative for access to this document Doc 358405 Montevina Small Form Factor SFF Platform Fern Hill DDR3 Customer Reference Board Schematic Contac...

Страница 16: ...d your request to intelsupport hibbertgroup com Please make sure to include in your e mailed request SKU Company Name Your Name first last Full mailing address Daytime Phone Number in case of question...

Страница 17: ...opment board in this kit may sometimes be referred to by its code name Fern Hill This manual will cover the features and details of the Fern Hill development board Note The Intel Core 2 Duo SU9400 pro...

Страница 18: ...8500 compatible o Port 80 display card o Power Supply o 80 GByte SATA Hard Disk Drive o DVD ROM Drive o Disk Drive Power and SATA Cables One HDMI and Display Port add in card codename Eaglemont One P...

Страница 19: ...tings Network Adapter and cables A Gigabit network interface is provided on the development board The network interface will not be operational until after all the necessary drivers are installed A st...

Страница 20: ...be installed near the equipment and should be readily accessible 2 To avoid shock ensure that the power cord is connected to a properly wired and grounded receptacle 3 Ensure that any equipment to whi...

Страница 21: ...power supply to the drive Connect the ATX power supply to the board at connector J4J1 The following steps need to be completed by the user 1 Attach the included CPU heatsink fan to the top of the CPU...

Страница 22: ...are a few limitations to development board operation when using the AC to DC power adapter mobile power mode First do not mix mobile and desktop power configurations Unplug the ATX power supply from c...

Страница 23: ...to shut down the system wait at least five seconds before turning the system on again to avoid damaging the system 2 8 System BIOS A version of the AMI BIOS is pre loaded on the development board Oth...

Страница 24: ...2 or Del and navigate to AMT and select disable b Navigate to Save changes and exit c Power off the system by pressing the power PWR button SW1C1 d Turn off the power supply remove power from the boar...

Страница 25: ...battery b Press the PWR button on the board The board will not power on but a couple of LEDs will flash c Switch the power supply off to power down the board d Remove the CMOS CLR jumper J5H2 16 Unplu...

Страница 26: ...board conforms to the ATX form factor The development board will fit in most standard ATX chassis A list of add in card connector and slot locations is provided in Section 4 1 Internal and rear panel...

Страница 27: ...DIMMs No ECC support Video One PCI Express Graphics Slot One dual channel LVDS Connector One VGA Connector One TV D Connector supporting S Video Composite video and Component video Spread spectrum cl...

Страница 28: ...ATA connector Both port 0 port 1 have interlock switch USB 12 USB 2 0 1 1 Ports 6 ports to back panel I O connector 5 ports to front panel I O connector and port to eSATA USB combo connector with resi...

Страница 29: ...l Wells powered M1 Main Well down Only Intel Management Engine power on M off Intel Management Engine powered off manageability power states Form Factor ATX 2 2 like form factor 10 layer board 8 layer...

Страница 30: ...is only licensed for evaluation purposes Refer to the documentation in your evaluation kit for further details on any terms and conditions that may be applicable to the granted licenses Customers usin...

Страница 31: ...al solution for installation on the processor This thermal solution has been tested in an open air environment at room temperature and is sufficient for development purposes The designer must ensure t...

Страница 32: ...es This processor also supports C2E and C4E Additionally the processor supports a new processor state Intel Deep Power Down Technology that brings the CPU leakage power down to the lowest possible DPW...

Страница 33: ...t an Intel HD Audio digital link PCI 2 3 compliant interface no slots on board slots provided on thimble peak card LPC bus six general purpose PCI Express 1 1a compliant lanes in which sixth PCI Expre...

Страница 34: ...ed as well Details of these stuffing options can be referred on page 19 of the Fern Hill schematics The TV is output through a D connector There are two cables in order to access TV a black D connecto...

Страница 35: ...a net detect event Slot 4 gets a switched Auxiliary 3 3 V supply 3 6 11 PCI Slots The reference board does not have any PCI slots on the motherboard Three 5V PCI slots are supported via the Thimble P...

Страница 36: ...d to MDC Card An on board header is provided at J9E2 and J9E4 for this purpose No direct connection is provided for the Intel High Definition Audio Card on the development board the Mott Canyon 4 card...

Страница 37: ...For jumper setting details refer to Section 4 3 1 Table 17 Note The eSATA drives should be externally powered Hence there is no power supply support for them on the motherboard 3 6 16 USB Connectors I...

Страница 38: ...PC slot at J8E1 A sideband header is provided at J9G1 for this purpose This sideband header also has signals for LPC power management Information on this header is on sheet 49 of the schematics and is...

Страница 39: ...SEL settings The BSEL settings can be manually changed via jumpers J1G5 J1G3 and J1G1 Refer to Table 17 The development board also supports PCIE CLKREQ through the DB800 SRC clock buffer U7C2 In addit...

Страница 40: ...Spec compliant power supply regardless of Vendor or wattage level an ATX12V rating means V5 min current 0 1 A ATX V5 min current 1 0 A among other differences For example the Sparkle Model No FSP300...

Страница 41: ...hange rework is necessary to get the older ITP tools to function properly Please contact an Intel representative for additional details 3 6 27 Board Form Factor The reference board form factor is simi...

Страница 42: ...XDP interface is backwards compatible with the ITP interface However an XDP to ITP converter cable is necessary to use the older ITP tools Also in some cases a resistor change rework is necessary to...

Страница 43: ...by using a high precision digital multi meter versus a standard digital multi meter is 33 times more accurate 2Table 15 summarizes all the power measurement sense resistors located on the board All se...

Страница 44: ...1 05M_A_SM R4R11 GMCH 1 5 V V1 5S V1 5S_TVDAC R5T15 GMCH 1 5 V V1 5 V1 5_DDR3_GMCH R5D2 GMCH 1 8 V V1 8S V1 8_DLVDS R5F4 GMCH 3 3 V V3 3S V3 3S_HV R5F2 GMCH 1 5 V V1 5S VCC_HDA R5F3 GMCH 3 3 V V3 3S_A...

Страница 45: ...CI R9D2 PCI 5 V V5S V5S_PCI R9B2 PCI 5 V V5 V5_PCI R8B3 PC IE 12 V V12S V12S_PCIESLOT1 R7N6 PCIe 12 V V12S V12S_PCIESLOT2 R7C24 PCIe 12 V V12S V12S_PCIESLOT3 R8B2 PCIe 12 V V12S V12S_PCIESLOT4 R8C4 PC...

Страница 46: ...V5A_USBPWR_IN2 R7H5 USB 5 V V5A V5A_USBPWR_IN1 R5W16 SPI 3 3 V V3 3M_WOL V3 3M_SPI R8R1 SATA 3 3 V V3 3S V3 3S_SATA_P0 R8Y1 SATA 5 V V5S V5S_SATA_P0 R8H12 SATA 12 V V12S V12S_SATA_P0 R8W14 SATA 3 3 V...

Страница 47: ...ies include Sparkle Model No FSP300 60BTVS meets this requirement and is an ATX12V 1 1 Spec note that this part may be End Of Life These 20 pin ATX power supplies may also work if you can t find the a...

Страница 48: ...Document Number 320249 001 4 Development Board Physical Reference 4 1 Board Components The following figure shows the major components of the Fern Hill development board 2...

Страница 49: ...Development Board Physical Reference Development Kit User s Manual 49 Table 16 gives a brief description of each component Figure 2 Fern Hill Development Board Components...

Страница 50: ...CR1B7 6 DB800 Clock Buffer U7C2 24 Front Panel Header J6H5 42 Manual VID Override Jumper J2B2 7 PCI Gold Fingers S9B1 25 SATA Cable Connect J6J3 J6J2 43 Teenah Cantiga SFF U5E1 8 PCI Express Slot3 J8...

Страница 51: ...connectors on the board Figure 3 Back Panel Connectors Item Description Ref Des Item Description Ref Des 1 RJ 45 LAN 2 USB Ports J5A1 5 VGA Bottom Side Connector Serial Port Top Side Connector J2A2 2...

Страница 52: ...Development Board Physical Reference 52 Development Kit User s Manual Figure 4 D Connector to Component Video Cable Figure 5 D Connector to Composite Video Cable Figure 6 D Connector to S Video Cable...

Страница 53: ...ote Some jumpers may fall off during shipment Jumpers that are only attached to one pin noted as 1 x are more prone to becoming detached Replacing detached 1 x jumpers is not required for proper board...

Страница 54: ...ower Enable 1 2 Hot plug removal supported 1 X Hot plug not supported 11 J5G1 SRTC RST 1 X Keep Intel Management Engine RTC registers 1 2 Clear Intel Management Engine RTC registers 12 J5H2 CMOS Clear...

Страница 55: ...ROGRAMMING SPI0 1 X 1 2 Program SPI 1 29 J9F2 KSC Enable 1 2 1 X 30 J9G2 Boot Block Programming 1 2 Normal Operation 1 X to Program the H8 31 J9H1 NMI 1 X 1 2 Disabled 32 J9H2 SATA interlock switch fo...

Страница 56: ...00 J1G5 open J1G3 open J1G1 2 3 4 4 Power and Reset Push Buttons The development board has two push buttons Power and Reset The Power button releases power to the entire board causing the board to boo...

Страница 57: ...utton switch SW8E1 to support wireless LAN network detection in S0 S5 This button is connected on the SMC KBC GPIO When pressed a manageability wake event is signaled to the ICH9M E SFF via SMC KBC ma...

Страница 58: ...Keyboard number lock CR9G1 Keyboard scroll lock CR9G3 Keyboard caps lock CR9G2 System State S0 CR5H4 System State S3 CR5H6 System State S4 CR5H7 System State S5 CR5H5 System State M0 M1 CR5H3 SATA Ac...

Страница 59: ...rogram the H8 1 Extract all files keep them in the same folder to a single directory of your choice on the host machine or on a floppy disk 2 Connect a NULL modem cable to the serial ports of each pla...

Страница 60: ...t 46 of the Fern Hill schematics Jumper Reference Designator Default Stuffing Option Programming Stuffing Option 1 Remote H8 Programming J7A1 J8B2 1 2 normal operation 2 3 link the Host Unit to On Boa...

Страница 61: ...plugs to the CRB through TPM header It also provides an additional 10 pin LPC header for LPC supported interfaces Port80 83 card decodes the LPC bus BIOS POST codes and displays on four 7 segment disp...

Страница 62: ...should be disabled in BIOS Upon boot up the system BIOS automatically detects that the PCI expansion card is present and connected to the system The system BIOS then performs all needed initializatio...

Страница 63: ...rk should use lead free solder in order to keep the board RoHS compliant 1 Resistors R5D7 R5D5 R5D3 R5C19 R5C16 R5C12 and R5C11 need to be taken off and placed in the ref des R5D6 R5D4 R5D R5C18 R5C17...

Страница 64: ...s R5B22 R5B19 R5B18 R5B16 R5B14 R5B11 R5B9 and R5B6 can be identified As mentioned in the procedure above these resistors needs to be taken off and assemble them in the ref des R5B21 R5B20 R5B17 R5B15...

Страница 65: ...rds should be re worked so that there are 100 k pull downs on all AUXP and AUXN signals There are only pull downs on AUX Eaglemont cards that are to be used for Display Port require this re work This...

Страница 66: ...up to two Intel HD Audio codecs simultaneously The Interposer plugs into any PCI Express or PCI slot for mechanical stability and is electrically connected to the platform via a 2x13 ribbon cable from...

Страница 67: ...2 of codecs Mapping of four ICH9M E SFF channels on MC4 card can be done using strapping resistors on the development board Three jumpers J27 J28 and J29 are used to select the appropriate SDATA_IN ch...

Страница 68: ...A 3 4 for MDC0 codec B 7 8 for MDC1 codec B 9 10 for MDC2 codec A J28 3 ACZ_SD_2 Destination MDC 0 1 2 9 10 for MDC2 codec A 1 2 for MDC0 codec A 3 4 for MDC0 codec B 5 6 for MDC1 codec A 7 8 for MDC...

Страница 69: ...nable both 34 mm and 54 mm ExpressCard functionality on the development board To support the PCI Express interface Duck Bay 3 plugs into PCI Express slot 0 J8C1 and PCI Express slot 2 J8D1 on the boar...

Страница 70: ...card specification Rev1 0 with USB connection enabled for each The USB interface is implemented using a separate cabling scheme The interposer supports a Bluetooth module and allows the concurrent usa...

Страница 71: ...V3 3 Closed 1 2 V3 3_aux Closed 2 3 Select V3 3 J6C1 1 X Channel data to slot0 Closed 1 2 Enable slot 1 Channel Data to BT through op amp J6C2 2 3 BT Pri_Clock to Slot0 Closed 1 2 Enable slot 1 Clock...

Страница 72: ...e Saddlestring II Fab 1 Users Guide for details on using each of these interfaces and reworks that may be required on the board The below table describes the reworks required for routing Display Port...

Страница 73: ...10 CAPC X5R 0402 10V 10 0 1uF IPN A36096 051 To route TX11 from Docking connector to MCH C6C12 CAPC X5R 0402 10V 10 0 1uF IPN A36096 052 To route TX11 from Docking connector to MCH C6D6 CAPC X5R 0402...

Страница 74: ...9 R7V24 and R7F7 All of the resistors should be of value 33 Figure 22 iHDMI Rework Instruction 2 B 2 Enabling the Integrated Trusted Platform Module iTPM 3 Populate a 2 2 k resistor at R1T7 on the bot...

Страница 75: ...uld use lead free solder in order to keep the board RoHS compliant B 4 Support for Upham 4 Stuff R8B5 and R7C1 Note All rework should use lead free solder in order to keep the board RoHS compliant B 5...

Страница 76: ...Rework Instructions 76 Development Kit User s Manual Figure 24 Low Voltage HD Audio Rework Sus Rail...

Страница 77: ...program the flash using a flash programming device 1 Setup the hardware and software of the flash programming device on a host system according to the manufacturer s instructions 2 Obtain the latest B...

Страница 78: ...the board and installing the heatsink fan assembly A heatsink is included in the kit To install the heatsink 1 If not done already attach the CPU fan to the top of the CPU heatsink with 4 screws The l...

Страница 79: ...development board around the processor See the figure below Be sure to orient the backplate so that it does not contact any of the decoupling capacitors The backplate is cut out on one side to allow t...

Страница 80: ...stallation 80 Development Kit User s Manual 6 Remove the tube of thermal grease from the package and use it to coat the exposed die of the CPU with the thermal grease See the figure below Figure 26 St...

Страница 81: ...Pick up the heatsink and squeeze the activation arm until it comes in contact with the base plate that is attached to the heatsink base This will cause the springs on the heatsink attachment mechanis...

Страница 82: ...he base of the heatsink Slide the heatsink over the lugs on the backplate pins so that the base is directly over the processor die and the pins on the backplate have travelled the entire length of the...

Страница 83: ...Kit User s Manual 83 9 Plug the fan connector for the heatsink onto the CPU fan header J2B3 on the motherboard See the figure below The CPU fan header J2B3 is a 3 pin connector with the words CPU Fan...

Страница 84: ...CPU Thermal Solution Heatsink Installation 84 Development Kit User s Manual 10 Once the thermal solution is in place the development kit is ready to use Figure 30 Step 10 Completed Assembly...

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