Development Board Features
Development Kit User’s Manual
41
3.6.26
Debug Interfaces
An XDP (Extended Debug Port) connector is provided at J1F1 for processor run control
debug support. This connector is compatible with both XDP and ITP-700. An external
adapter is used to interface ITPFlex700 cable to the platform. XDP incorporates new
run-control features on the JTAG interface and allows the user to communicate with
the processor or GMCH.
A port 80-83 display add-in card can also be used for debug. The port 80-83 add in
card could be used on the TPM header located at J9A1
Note:
The XDP interface is backwards compatible with the ITP interface. However, an XDP to
ITP converter cable is necessary to use the older ITP tools. Also, in some cases a
resistor change rework is necessary to get the older ITP tools to function properly.
Please contact an Intel representative for additional details.
3.6.27
Board Form-Factor
The reference board form factor is similar to the full-size ATX specification. The board
is 10 layers and measures 12 inches x 10.2 inches.
3.7
Power Management
3.7.1
Power Management States
Table 12 and Table 13 list the power management states that have been defined for
the development board. The system’s Controller Link (CL) operates at various power
level, called the M-states. M0 is the highest power state, followed by M1 and M-off.
Table 12. System Power Management States
State
Description
G0/S0/C0 Full
on
G0/S0/C2 Quick
Start:
STPCLK# signal active
G0/S0/C3
Deep Sleep: CPUSTP# signal active
G0/S0/C4-C6
Deeper Sleep: Voltage to processor core is lowered (feature enabled by
software)
G1/S3
Suspend To RAM (all switched rails are turned off)
G1/S4
Suspend To Disk
G2/S5 Soft
Off
G3 Mechanical
Off
