Intel BX80571E7500 - Core 2 Duo 2.93 GHz Processor, Руководство по программированию

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I
NTEL
® X
EON
® P
ROCESSOR
7500 S
ERIES
U
NCORE
P
ROGRAMMING
G
UIDE
UNCORE PERFORMANCE MONITORING
2-45
2.5 S-Box Performance Monitoring
2.5.1 Overview of the S-Box
The S-Box represents the interface between the last level cache and the system interface. It manages
flow control between the C and R & B-Boxes. The S-Box is broken into system bound (ring to Intel QPI)
and ring bound (Intel QPI to ring) connections.
As such, it shares responsibility with the C-Box(es) as the Intel QPI caching agent(s). It is responsible
for converting C-box requests to Intel QPI messages (i.e. snoop generation and data response
messages from the snoop response) as well as converting/forwarding ring messages to Intel QPI
packets and vice versa.
2.5.2 S-Box Performance Monitoring Overview
Each S-Box in the Intel Xeon Processor 7500 Series supports event monitoring through 4 48b wide
counters (S_MSR_PMON_CTR/CTL{3:0}). Each of these four counters can be programmed to count any
S-Box event. the S-Box counters can increment by a maximum of 64 per cycle.
The S-Box also includes a mask/match register that allows a user to match packets leaving the S-Box
according to various standard packet fields such as message class, opcode, etc. (NOTE: specifically
goes with event 0, does not effect other events)
For information on how to setup a monitoring session, refer to
Section 2.1, “Global Performance
Monitoring Control”
.
2.5.2.1 S-Box PMU - Overflow, Freeze and Unfreeze
If an overflow is detected from a S-Box performance counter, the overflow bit is set at the box level
(S_MSR_PMON_GLOBAL_STATUS.ov), and forwarded up the chain to the U-Box where it will be stored
in U_MSR_PMON_GLOBAL_STATUS.ov_s0. Each S-Box collects overflow bits for all boxes on it’s ‘side’ of
the chip. Refer to
Table 2-26, “S_MSR_PMON_SUMMARY Register Fields” to determine how these bits
are accumulated before they are forwarded to the U-Box.
HW can be also configured (by setting the corresponding .pmi_en to 1) to send a PMI to the U-Box
when an overflow is detected. The U-Box may be configured to freeze all uncore counting and/or send a
PMI to selected cores when it receives this signal.
Once a freeze has occurred, in order to see a new freeze, the overflow field responsible for the freeze,
must be cleared by setting the corresponding bit in S_MSR_PMON_GLOBAL_OVF_CTL.clr_ov. Assuming
all the counters have been locally enabled (.en bit in data registers meant to monitor events) and the
overflow bit(s) has been cleared, the S-Box is prepared for a new sample interval. Once the global
controls have been re-enabled (
Section 2.1.4, “Enabling a New Sample Interval from Frozen
Counters” ), counting will resume.
Note: Due to the nature of the subcounters used in the S-Box, if a queue occupancy count
event is set up to be captured, SW should set .reset_occ_cnt in the same write that the
corresponding control register is enabled.
2.5.3 S-BOX Performance Monitors
Table 2-25. S-Box Performance Monitoring MSRs
MSR Name Access
MSR
Address
Size
(bits)
Description
SS1_CR_S_MSR_MASK RW_RO 0x0E5A 64 S-Box 1 Enable Mask Register
SS1_CR_S_MSR_MATCH RW_RO 0x0E59 64 S-Box 1 Enable Match Register
SS1_CR_S_MSR_MM_CFG RW_NA 0x0E58 64 S-Box 1 Enable Match/Mask Config