Intel® 460GX Chipset System Software Developer’s Manual
v
6.1.6
Private Bus between SAC and SDC .....................................................6-2
6.2
Memory ECC Routing ........................................................................................6-3
6.3
Data Poisoning ...................................................................................................6-3
6.4
Usage of First-error and Next-error ....................................................................6-3
6.4.1
Masked Bits...........................................................................................6-4
6.4.2
BERR#/BINIT# Generation ...................................................................6-4
6.4.3
INTREQ#...............................................................................................6-4
6.4.4
XBINIT#.................................................................................................6-5
6.4.5
XSERR# ................................................................................................6-5
6.5
SAC/SDC Errors.................................................................................................6-5
6.5.1
Data ECC or Parity Errors .....................................................................6-5
6.5.2
System Bus Errors ................................................................................6-6
6.5.3
SAC to SDC Interface Errors.................................................................6-6
6.5.4
SAC to MAC Interface Errors ................................................................6-7
6.5.5
SDC/Memory Card Interface Errors ......................................................6-7
6.5.6
SDC/System Bus Errors........................................................................6-8
6.5.7
SDC Internal Errors ...............................................................................6-8
6.6
Error Determination ............................................................................................6-8
6.6.1
SAC Address on an Error......................................................................6-9
6.6.2
SDC Logging Registers.......................................................................6-10
6.7
Clearing Errors .................................................................................................6-11
6.7.1
SAC/SDC Error Clearing .....................................................................6-11
6.8
Multiple Errors ..................................................................................................6-11
6.8.1
SDC Multiple Errors.............................................................................6-12
6.8.2
SAC Multiple Errors.............................................................................6-13
6.8.3
Single Errors with Multiple Reporting ..................................................6-13
6.8.4
Error Anomalies...................................................................................6-13
6.9
Data Flow Errors ..............................................................................................6-14
6.10
Error Conditions ...............................................................................................6-15
6.10.1 Table of Errors.....................................................................................6-15
6.11
PCI Integrity......................................................................................................6-20
6.11.1 PCI Bus Monitoring .............................................................................6-20
6.11.2 PXB as Master ....................................................................................6-20
6.11.3 PXB as Target .....................................................................................6-21
6.11.4 GXB Error Flow ...................................................................................6-22
6.12
WXB Data Integrity and Error Handling............................................................6-26
6.12.1 Integrity................................................................................................6-26
6.12.2 Data Parity Poisoning..........................................................................6-26
6.12.3 Usage of First Error and Next Error Registers ....................................6-26
6.12.4 Error Mask Bits....................................................................................6-27
6.12.5 Error Steering/Signaling ......................................................................6-27
6.12.6 INTRQ# Interrupt.................................................................................6-29
6.12.7 Error Determination and Logging ........................................................6-29
6.12.8 Error Conditions ..................................................................................6-30
7
AGP Subsystem ..............................................................................................................7-1
7.1
Graphics Address Relocation Table (GART) .....................................................7-1
7.1.1
GART Implementation ...........................................................................7-3
7.1.2
Programming GART..............................................................................7-4
7.1.3
GART Implementation ...........................................................................7-5
7.1.4
Coherency .............................................................................................7-5
7.1.5
Interrupt Handling..................................................................................7-6
Содержание 460GX
Страница 1: ...Intel 460GX Chipset System Software Developer s Manual June 2001 Document Number 248704 001 ...
Страница 20: ...Introduction 1 8 Intel 460GX Chipset Software Developer s Manual ...
Страница 80: ...System Architecture 3 8 Intel 460GX Chipset Software Developer s Manual ...
Страница 90: ...System Address Map 4 10 Intel 460GX Chipset Software Developer s Manual ...
Страница 98: ...Memory Subsystem 5 8 Intel 460GX Chipset Software Developer s Manual ...
Страница 146: ...AGP Subsystem 7 16 Intel 460GX Chipset Software Developer s Manual ...
Страница 170: ...IFB Register Mapping 9 6 Intel 460GX Chipset Software Developer s Manual ...
Страница 190: ...IFB Usage Considerations 10 20 Intel 460GX Chipset Software Developer s Manual ...
Страница 232: ...LPC FWH Interface Configuration 11 42 Intel 460GX Chipset Software Developer s Manual ...
Страница 244: ...IDE Configuration 12 12 Intel 460GX Chipset Software Developer s Manual ...
Страница 258: ...Universal Serial Bus USB Configuration 13 14 Intel 460GX Chipset Software Developer s Manual ...
Страница 270: ...SM Bus Controller Configuration 14 12 Intel 460GX Chipset Software Developer s Manual ...
Страница 288: ...PCI LPC Bridge Description 15 18 Intel 460GX Chipset Software Developer s Manual ...
Страница 294: ...IFB Power Management 16 6 Intel 460GX Chipset Software Developer s Manual ...