Operation Manual HORIBA APDA-371
Particulate Monitor
Date:
April, 2010
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HORIBA Europe GmbH, Julius-Kronenberg-Str. 9, D-42799 Leichlingen,
: +49(0)2175-8978-0,
: +49(0)2175-8978-50
Page 56
8.2
Early Cycle Mode Description
During a standard APDA-371 measurement cycle, the unit waits for the beginning of the new hour before it sets the
analog output to represent the just-finished hour’s concentration. However, some types of dataloggers (such as ESC)
must have the concentration value available before the new hour starts, or the data will be stored in the wrong hour.
The APDA-371 has a special EARLY cycle mode (in the SETUP > INTERFACE menu) which causes the unit to start
and finish the measurement a few minutes early in order to output the concentration voltage for the last 5-minutes of the
hour which was just sampled. The datalogger must be programmed to read this value during the window. The APDA-
371 clock and the datalogger clock will usually need to be synchronized because of the critical timing involved. The
following describes the timing of the STANDARD and EARLY modes.
STANDARD Cycle Example
EARLY Cycle Example
Analog Output Levels
C
0
represents the concentration output level measured from time T
0
to T
1
, where the T labels represent the top
(beginning) of an hour (such as 12:00:00). As you can see, the concentration voltage C
0
for the standard cycle is
present for the whole next hour following the measurement. In early mode the C
0
voltage for the current hour is present
for only the last 5 minutes of the hour just-sampled (minute 55 to 60), and all other times the concentration output
voltage is 0.920 volts.
External Reset Windows
An external reset signal may be used to synchronize the APDA-371 clock to the datalogger. In standard mode the
external reset window is plus or minus 5 minutes around the beginning of the hour, but in early mode the external reset
window is between minute 50 and 60 only. The clock will not reset if the cycle has not reached the I
3
count. The error
log will contain the date and time of the reset attempt. If the I
3
count is in progress, or the cycle is past the I
3
count, then
the measurement cycle is canceled. The error log will contain the date and time of the reset. A canceled cycle will also
force the analog output to the full-scale values (1.000 volts in standard mode, or 0.920 volts in early mode).
Standard Mode Clock Resets:
Minute 0 to 5: An external reset signal will change the APDA clock back to the 00:00 of the current hour. If a cycle has
already started, it will continue. No error occurs since there is adequate time to complete the cycle.
Minute 5 to 55: An external reset signal has no effect. The error log will contain the date and time of the reset attempt.
Minute 55 to 60:
If an external reset occurs after a completed cycle (idle condition), then no error occurs. The
clock will be set forward to 00:00 of the next hour and a new measurement cycle will start.
