Rev. 1.71
100
April 11, 2017
Rev. 1.71
101
April 11, 2017
HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
•
SADC2 Register
Bit
7
6
5
4
3
2
1
0
Name
ENOPA
VBGEN
—
—
SAVRS3 SAVRS2 SAVRS1 SAVRS0
R/W
R/W
R/W
—
—
R/W
R/W
R/W
R/W
POR
0
0
—
—
0
0
0
0
Bit 7
ENOPA
: OPA enable/disable control register
0: OPA disable
1: OPA enable
Bit
6
VBGEN
: Bandgap buffer disable/enable control bit
0: Bandgap buffer disable
1: Bandgap buffer enabl
e
Bit 5~4
Unimplemented, read as "0"
Bit 3~0
SAVRS3~SAVRS0
: ADC reference voltage selection bit
0000: ADC reference voltage comes from AV
DD
0001: ADC reference voltage comes from V
REF
0010: ADC reference voltage comes from V
REF
×
2
0011: ADC reference voltage comes from V
REF
×
3
0100: ADC reference voltage comes from V
REF
×
4
1001: Inhibit to use
1010: ADC reference voltage comes from V
BG
×
2
1011: ADC reference voltage comes from V
BG
×
3
1100: ADC reference voltage comes from V
BG
×
4
Other Values: same as 0000
Note: (1) When Select V
REF
or V
REF
×
2 or V
REF
×
3 or V
REF
×
4 as ADC reference voltage,
HT66F002/HT66F0025: pin share control bits (PAS3, PAS2) is (1, 0) to select VREF as input.
HT66F003: pin share control bits (PAS2, PAS1) is (1, 0) to select VREF as input.
HT66F004: pin share control bits (PAS3, PAS2) is (1, 0) to select VREF as input
(2) V
BG
=1.04V
(3) When SAVRS3=1, OPA selects V
BG
as input.
(4) If the programs select external reference voltage V
REF
and the internal reference
voltage V
BG
as ADC reference voltage, then the hardware will only choose the internal
reference voltage V
BG
as an ADC reference voltage input.
A/D Operation
The START bit is used to start and reset the A/D converter. When the microcontroller sets this bit
from low to high and then low again, an analog to digital conversion cycle will be initiated. When
the START bit is brought from low to high but not low again, the ADBZ bit in the SADC0 register
will be cleared to zero and the analog to digital converter will be reset. It is the START bit that is
used to control the overall start operation of the internal analog to digital converter.
The ADBZ bit in the SADC0 register is used to indicate whether the analog to digital conversion
process is in process or not. When the A/D converter is reset by setting the START bit from
low to high, the ADBZ flag will be cleared to 0. This bit will be automatically set to “1” by the
microcontroller after an A/D conversion is successfully initiated. When the A/D conversion is
complete, the ADBZ will be cleared to 0. In addition, the corresponding A/D interrupt request flag
will be set in the interrupt control register, and if the interrupts are enabled, an appropriate internal
interrupt signal will be generated. This A/D internal interrupt signal will direct the program flow to
the associated A/D internal interrupt address for processing. If the A/D internal interrupt is disabled,
the microcontroller can be used to poll the ADBZ bit in the SADC0 register to check whether it has
been cleared as an alternative method of detecting the end of an A/D conversion cycle.
