Holtek HT66F002, Руководство пользователя

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Rev. 1.71 70 April 11, 2017 Rev. 1.71 71 April 11, 2017
HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Standard Type TM Register Description
Overall operation of the Standard TM is controlled using series of registers. A read only register
pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store
the internal 10-bit CCRA value. The remaining two registers are control registers which setup the
different operating and control modes as well as three CCRP bits.
Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
STM0C0 ST0PAU ST0CK2 ST0CK1 ST0CK0 ST0ON ST0RP2 ST0RP1 ST0RP0
STM0C1 ST0M1 ST0M0 ST0IO1 ST0IO0 ST0OC ST0POL ST0DPX ST0CCLR
STM0DL D7 D6 D5 D4 D3 D2 D1 D0
STM0DH — — — — — — D9 D8
STM0AL D7 D6 D5 D4 D3 D2 D1 D0
STM0AH — — — — — — D9 D8
10-bit Standard TM Register List
STM0C0 Register
Bit 7 6 5 4 3 2 1 0
Name ST0PAU ST0CK2 ST0CK1 ST0CK0 ST0ON ST0RP2 ST0RP1 ST0RP0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0
bit 7 ST0PAU : STM Counter Pause Control
0: Run
1: Pause
The counter can be paused by setting this bit high. Clearing the bit to zero restores normal
counter operation. When in a Pause condition the STM will remain powered up and continue to
consume power. The counter will retain its residual value when this bit changes from low to high
and resume counting from this value when the bit changes to a low value again.
bit 6~4 ST0CK2~ST0CK0 : Select STM Counter clock
000: f
SYS
/4
001: f
SYS
010: f
H
/16
011: f
H
/64
100: f
TBC
101: f
TBC
110: STCK0 rising edge clock
111: STCK0 falling edge clock
These three bits are used to select the clock source for the STM. The external pin clock source
can be chosen to be active on the rising or falling edge. The clock source f
SYS
is the system clock,
while f
H
and f
TBC
are other internal clocks, the details of which can be found in the oscillator
section.
bit 3
ST0ON
: STM Counter On/Off Control
0: Off
1: On
This bit controls the overall on/off function of the STM. Setting the bit high enables the counter
to run, clearing the bit disables the STM. Clearing this bit to zero will stop the counter from
counting and turn off the STM which will reduce its power consumption. When the bit changes
state from low to high the internal counter value will be reset to zero, however when the bit
changes from high to low, the internal counter will retain its residual value until the bit returns
high again. If the STM is in the Compare Match Output Mode or the PWM output Mode or
Single Pulse Output Mode then the STM output pin will be reset to its initial condition, as
specified by the ST0OC bit, when the ST0ON bit changes from low to high.