Rev. 1.00
56
March 24, 2020
Rev. 1.00
57
March 24, 2020
BS83A04C
4-Key Enhanced Touch I/O Flash MCU
BS83A04C
4-Key Enhanced Touch I/O Flash MCU
requested by the CTIO1~CTIO0 bits must be different from the initial value setup
using the CTOC bit otherwise no change will occur on the CTM output pin when a
compare match occurs. After the CTM output pin changes state it can be reset to its
initial level by changing the level of the CTON bit from low to high.
In the PWM Output Mode, the CTIO1 and CTIO0 bits determine how the CTM output
pin changes state when a certain compare match condition occurs. The PWM output
function is modified by changing these two bits. It is necessary to change the values of
the CTIO1 and CTIO0 bits only after the CTM has been switched off. Unpredictable
PWM outputs will occur if the CTIO1 and CTIO0 bits are changed when the CTM is
running.
Bit 3
CTOC
: CTM CTP Output control bit
Compare Match Output Mode
0: Initial low
1: Initial high
PWM Output Mode
0: Active low
1: Active high
This is the output control bit for the CTM output pin. Its operation depends upon
whether CTM is being used in the Compare Match Output Mode or in the PWM
Output Mode. It has no effect if the CTM is in the Timer/Counter Mode. In the
Compare Match Output Mode, it determines the logic level of the CTM output pin
before a compare match occurs. In the PWM Output Mode it determines if the PWM
signal is active high or active low.
Bit 2
CTPOL
: CTM CTP Output polarity Control
0: Non-invert
1: Invert
This bit controls the polarity of the CTM output pins. When the bit is set high the
CTM output pins will be inverted and not inverted when the bit is zero. It has no effect
if the CTM is in the Timer/Counter Mode.
Bit 1
CTDPX
: CTM PWM period/duty Control
0: CCRP – period; CCRA – duty
1: CCRP – duty; CCRA – period
This bit determines which of the CCRA and CCRP registers are used for period and
duty control of the PWM waveform.
Bit 0
CTCCLR
: CTM Counter clear condition selection
0: CTM Comparatror P match
1: CTM Comparatror A match
This bit is used to select the method which clears the counter. Remember that the
Compact TM contains two comparators, Comparator A and Comparator P, either of
which can be selected to clear the internal counter. With the CTCCLR bit set high,
the counter will be cleared when a compare match occurs from the Comparator A.
When the bit is low, the counter will be cleared when a compare match occurs from
the Comparator P or with a counter overflow. A counter overflow clearing method can
only be implemented if the CCRP bits are all cleared to zero. The CTCCLR bit is not
used in the PWM Output Mode.
• CTMDL Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
Bit 7~0
D7~D0
: CTM Counter Low Byte Register bit 7 ~ bit 0
CTM 10-bit Counter bit 7 ~ bit 0