Holtek BC45B4523, Руководство пользователя, Страница: 8 / 96

Rev. 1.20 8 October 28, 2020
BC45B4523
Peripheral Specifications
Block Properties Min. Typ. Max. Unit
FIFO Total Size — 64 — Byte
Program Timer
Time Count — — 39.6 Sec
Trigger Source TxStart, TxStop, RxStart, RxStop, User —
Wake Up Timer
Time Count (for WkUpCD) 61.0μs — 1 day —
Timer Accuracy -1.5 — +1.5 %
Trigger Source User configuration —
Interrupt
Trigger Source — —
Output Level Toggle High, Toggle Low —
Crystal Requirement
Symbol XTAL Spec Min. Typ. Max. Unit
f
XTAL
Frequency — 27.12 — MHz
TOL Frequency Tolerance — — ±30 ppm
C
LOAD
Load Capacitance — 10 — pF
ESR Equivalent Series Resistance — — 120 Ω
Functional Overview
The BC45B4523 contains a transmitter, a receiver,
a baseband processor and a voltage regulator. The
functional block diagram of the device is shown in the
Block Diagram chapter.
The transmitter contains integrated dual drivers,
supporting operating voltage from 2.7V to 5.5V.
The transmitter can be configured to support various
antenna topologies such as differential driving, single-
ended driving and pre-driving for external Class-E
amplifiers. An on-chip coder can generate a variety
of line-coding, namely Miller to support ISO14443A,
NRZ to support ISO14443B, and 1-of-4 and 1-of-256
to support ISO15693. Moreover, a direct modulation
from pin TD is allowed.
The receiver consists of an on-chip envelope detector,
a voltage reference generator, an on-chip oscillator, an
amplifier & filter system, a filter tuning system, a BPSK
bit decoder, a Manchester-and-FSK bit decoder, a frame
decoder and a timing control generator. A receiver
input, pin RX, can accept a carrier modulated signal
or an envelope-demodulated signal from an external
envelope detector. Employing an external envelope
detector can yield an extended read range. With this
flexibility, it enables a wide variety of RF connection
topologies. The envelope of the input signal is filtered
and amplified with optional control by an automatic
gain control (AGC), resulting in an amplitude control
to prevent shape distortion. The BPSK bit decoder
and Manchester-and-FSK bit decoder translates the
amplified signal to the digital data. The bit data is then
checked the validity and assembled into bytes by the
digital frame decoder. Next, the complete and valid
bytes are transferred into the FIFO. In case of the
encryption, the Crypto_M engine is provided to encrypt
and decrypt as well as execute the authentication
process for the Crypto_M card.
The digital part contains an FIFO controller, a CRC
generator, a programmable timer, a wake-up timer, a
state machine, a wake-up controller and configurable
registers in order to facilitate RF transmission
and reception activities. The BC45B4523 can be
controlled and accessed through a 4-wire SPI interface
and register pages with the communication speed of
up to 10Mbps. An interrupt system and a pin IRQ are
provided to support interrupt-oriented programming
after the end of RF activities.
In addition, there are two regulators, 3.3V and 1.6V
output. The 3.3V regulator is applied for supplying
external load, MCU or analog parts itself with 150mA
driving capability. The 1.6V output is regulated
voltage from pin IO_VDD to D_VDD for supplying
digital circuit itself.
Typical Operating Circuit
A basic operating circuit and a typical usage are
illustrated in the following figures. A differential
antenna is directly connected to the transmitter driver
of the BC45B4523, whereas the receiver senses the
tag-modulated signal from the envelope of RF carrier
through the voltage divider. The device is controlled
by a microcontroller via an SPI interface. In addition,
other circuit configurations such as Class-E amplifiers
with external envelope detectors or single-ended
drivers can be implemented and will be described in
the “Circuit Configuration” section.