Rev. 1.20
35
October 28, 2020
BC45B4523
• FDThreshold_Q_H Register
This register is used to setup the threshold level phase Q for field detection operation.
Address
Bit
7
6
5
4
3
2
1
0
0x33
Name
FDThreshold_Q_H[7:0]
Type
R/W
Reset Value
0
0
1
0
0
0
0
0
Bit 7~0
FDThreshold_Q_H[7:0]
:
This bit field is used to define threshold level phase Q for external RF field, if ADC_Result_Q >
FDThreshold_Q_H, RxIRq will be set when condition is matched following FDIRqCfg.
• CDThreshold_I_L Register
This register is used to setup the low threshold level phase I for card detection operation.
Address
Bit
7
6
5
4
3
2
1
0
0x34
Name
CDThreshold_I_L[7:0]
Type
R/W
Reset Value
0
1
0
0
0
0
0
0
Bit 7~0
CDThreshold_I_L[7:0]
:
This bit field is used to define threshold level phase I for card detection operation, when card is loaded
to RF field driven by the device itself. If ADC_Result_I < CDThreshold_I_L or ADC_Result_I >
CDThreshold_I_H, CDIRq will be set when condition is matched following CDIRqCfg.
• CDThreshold_I_H Register
This register is used to setup the high threshold level phase I for card detection operation.
Address
Bit
7
6
5
4
3
2
1
0
0x35
Name
CDThreshold_I_H[7:0]
Type
R/W
Reset Value
1
0
0
0
0
0
0
0
Bit 7~0
CDThreshold_I_H[7:0]
:
This bit field is used to define threshold level phase I for card detection operation, when card is loaded
to RF field driven by the device itself. If ADC_Result_I < CDThreshold_I_L or ADC_Result_I >
CDThreshold_I_H, CDIRq will be set when condition is matched following CDIRqCfg.
• CDThreshold_Q_L Register
This register is used to setup the low threshold level phase Q for card detection operation.
Address
Bit
7
6
5
4
3
2
1
0
0x36
Name
CDThreshold_Q_L[7:0]
Type
R/W
Reset Value
0
1
0
0
0
0
0
0
Bit 7~0
CDThreshold_Q_L[7:0]
:
This bit field is used to define threshold level phase Q for card detection operation, when card is loaded
to RF field driven by the device itself. If ADC_Result_Q < CDThreshold_Q_L, ADC_Result_Q >
CDThreshold_Q_H, CDIRq will be set when condition is matched following CDIRqCfg.