Design-In - Electrical Aspects
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COMX Communication Modules | Design Guide
DOC100901DG18EN | Revision 18 | English | 2013-12 | Released | Public
© Hilscher, 2002-2013
3.1.8.7
Timing Diagram parallel Dual-Port Memory Interface
The following diagram shows the timing for dual-port memory read access.
Figure 9: COMX Timing Diagram for Read Access
The following diagram shows the timing for dual-port memory write access.
Figure 10: COMX Timing Diagram for Write Access
Description and values are on the next page.