Design-In - Electrical Aspects
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COMX Communication Modules | Design Guide
DOC100901DG18EN | Revision 18 | English | 2013-12 | Released | Public
© Hilscher, 2002-2013
3.1.4
COMX Pinning of the System Bus Connector X1 – Serial Mode
The following table is valid for COMX 10 and COMX 51 Modules only and if the serial dual-port
memory mode is active.
X1
Pin Signal
COMX 10
PAD Type
COMX 51
PAD Type
Symbol
Type
1 reserved
IOU6
IOD9
reserved
Note
3
2 reserved
IOU6
IOU9
reserved
Note
3
3 reserved
IOD6
IOU9
reserved
Note
3
4 reserved
IOD6
IOU9
reserved
Note
3
5 reserved
IOD6
IOU9
SPM_SIRQn LVTTL Output,
Note 4
6 reserved
IOD6
IOU9
SPM_DIRQn LVTTL Output,
Note 4
7 Clock
IOD6
IOU9
SPM_CLK
LVTTL
Input
8
Chip select, active low
IOD6
IOU9
SPM_CSn
LVTTL Input
9
Master Out Slave In
IOD6
IOU9
SPM_MOSI
LVTTL Input
10
Master In Slave Out
IOD6
IOU9
SPM_MISO
LVTTL Output
11 Ground
GND
12 Power
Supply
+3V3
13
Transmit Data,
Serial line
IOUS6 IODS6
UART1_TXD LVTTL
Output
14
Receive Data, Serial line
IOUS6
IODS6
UART1_RXD
LVTTL Input
15
Request to Send,
Serial line & SYNC0
IOUS6 IODS6
UART1_RTSn /
SYNC0
LVTTL Output /
SYNC Output Signal
XC3_IO0 (Note 1, 2)
16
Clear to Send,
Serial line & SYNC1
IOUS6 IODS6
UART1_CTSn /
SYNC1
LVTTL Input /
SYNC Output Signal
XC3_IO1 (Note 1, 2)
17
USB positive,
Diagnostic line
USB USB
USB+
USB
18
USB negative,
Diagnostic line
USB USB
USB-
USB
19
Receive Data,
Diagnostic line
IOUS6 IODS6
UART0_RXD LVTTL
Input
20
Transmit Data,
Diagnostic line
IOUS6 IODS6
UART0_TXD LVTTL
Output
21
Reset, active low
IUS
DPM_RESETn
LVTTL Input; 10 k
Ω
pull up
22 reserved
IOU6
reserved
Note
3
23
Host mode selection at
start-up
IOU6 IOU9
DPM_DIRQn
At
start-up:
LVTTL Input
24 reserved
IOU6
IOU9
reserved
Note
3
25 reserved
IOU6
IOU9
reserved
Note
3
26 reserved
IOU6
IOU9
reserved
Note
3
Table 23: COMX Pinning of the System Bus Connector X1- Serial DPM Mode COMX 10/COMX 51 (Part 1)