Host Interface
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COM-C | Communication Module
DOC021001DG12EN | Revision 12 | English | 2011-06 | Released | Public
© Hilscher, 2002-2011
3.4.4
Address Bus and Data Bus
These signal lines contain the address bus lines A0 till A13 and data bus lines D0 up to D15 of the
Dual-port memory. The address and data lines are non-multiplexed. Generally the COM devices
use only an 8 Bit data bus (signals D0-D7) but the signals D8-D15, BHE# and WIF# are not con-
nected.
The COM-CA-SCEB devices support additional data bus lines to drive a 16 Bit data interface. If
your host interface can support 16 Bit you should connect the WIF# signal to ground. If not please
let this uncommitted that 16 Bit modules will work in a compatible 8 Bit mode.
In case of a 16 Bit system you have to generate the BHE# and A0 signal according the following
table.
BHE#
A0
Function
0 0 word
access
0 1 access
high
byte
1 0 access
low
byte
1 1 no
access
Table 24: Function Table of the 16 Bit Decode Logic
3.4.5
Dual-Port Memory Control Lines
The user has to integrate the Dual-port memory by mapping the memory space of the Dual-port
memory into the address range of the host system.
The access to the Dual-port memory is handled over the control lines write WR#, read RD# and
Chip select CS# and could be like standard static RAM. All signals are low active.
