12/20/11
888-2595-001
4-15
WARNING: Disconnect primary power prior to servicing.
Section 4 Theory of Operation
ZX Series
compared by U25A against a fixed +2V reference from network R109-CR17-C16-R64
unless it is overridden by stronger signal through the diode-or network.
•
Reverse power sample from JP1-U24A-CR9 forces the APC to follow the
reverse power level (reverse foldback)
•
Logic high from TX_OFF_STAT via CR10 forces the APC output to zero
when the transmitter is off.
•
Logic high from MUTE_FAULT via CR12 forces the APC output to zero
when a mute is being requested via the remote control or FlexStar exciter
when changing modes.
The output of U25A adjusts the transmitter output power level via R-C ramp circuit
R20-C66-U25B and the power control PWR_CTL signal line. This line is either used
by the exciter to set its output power level in linear IBOC applications or the IPA bias
level in non-linear FM-only applications. Steering diode CR11 allows the PWR_CTL
line to be shared by multiple amplifier chassis in multi-amp applications. In such cases,
the exciter power setting or IPA bias would following only the highest PWR_CTL level
from the multiple chassis.
An APC idle circuit, formed by Q15, R133, R137, Q14, and R135, clamps the power
control voltage to a user-adjustable maximum level whenever a PA module is shut
down anywhere in the transmitter.In practice, the APC IDLE circuit is typically
adjusted so that the average PA module current remains constant both before and after
the first PA module is removed at the highest gain frequency. For frequency agile
transmitters in N+1 applications, this adjustment is typically performed at the highest
gain channel.
Level shifting amplifier U28C shifts the 0 to +3.5V output of U25B to a 0V to -15V
level suitable for controlling the gain of the IPA. Jumper JP3 allows the IPA bias level
to be variable in the case of FM-only amplification or equal to a fixed 0V level PA bias
in the case of IBOC amplification where the exciter controls the transmitter power.
In summary, the complete APC loop is as follows:
1.
Transmitter output
2.
Forward power sample and detector on I/O board.
3.
Raise/lower VGA (U27C)
4.
Max power set VGA (U24B)
5.
Diode-or network (CR6, CR9, CR10, CR12)
6.
APC comparator (U25A)
7.
Ramp circuit (U25B)
Содержание ZX10
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Страница 80: ...3 12 888 2595 001 12 20 11 WARNING Disconnect primary power prior to servicing Section 3 Operation ZX Series ...
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