Harris Platinum HT EL 2000LS, Техническое руководство

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sample selected and the decimal point selection for the digital
display. The enable line (EN_SQ, EN_VOLT, EN_CUR) to the
multiplexers is asserted HI and the decimal points (DP1*, DP2*,
DP3*) are asserted low to turn on the display decimal point.
NOTE: The (*) character is used to denote a signal is asserted
LOW when true.
Table 4-1 shows the address of A0, A1, & A3 (ADR) the three
bit meter selection counter coupled to the functions displayed.
4.3.5
Loss Of Video Delay Detector
The Loss of Video Delay Detector, page two, is made up of U8
through U14 to form a function “on” video present delay of 3.5
to 9.2 seconds and on video loss a delay of 1 to 2.7 minutes. The
function can be inhibited by placing JP1 in the 2-3 position or
enabled in the 1-2 position.
With JP1 in the NORMAL (1-2) position and video present the
reset to U11-6 is asserted low allowing the oscillator in U11 to
run starting a terminal count of 32768. This will assert U11-8 Hi
which clocks U13-3 (D latch) Hi causing U13-5 to change to the
state of the D input which is Hi. This will assert U13-6 low
causing U14-1 to assert Hi signaling the delayed presence of
video and un-mute the rf mute circuit.
On the loss of video U11-6 is asserted Hi resetting the video
present counter and U12-6 is asserted low allowing U12 to start
counting. At the time between loss of video and the terminal
count of U12 the visual rf level is reduced by asserting U16-18
low which inserts R41 CW LEVEL SET pot in the visual power
control circuit. At the terminal count of 32768 U12-8 will assert
Hi causing U14-10 to assert low causing U13-1 to reset the D
latch asserting U13-6 Hi causing U14-1 low signaling the de-
layed loss of video which will rf mute exciter output.
4.3.6
Override/Normal Selection
Located in the upper right hand corner of the meter board is JP1
NORMAL/OVERRIDE jumper selection. In the NORMAL po-
sition the delay timers operate as outlined above. In the OVER-
RIDE position both delay timers are inhibited and the loss of
video signal is passed through U14 to rf mute circuit of the
exciter.
4.3.7
Clock Circuits
Sheet 4 of the schematic shows the clock PALs for the up/down
counters for VISUAL RAISE/LOWER U18, AURAL
RAISE/LOWER U19, METER CLOCK U20, and METER SE-
LECT U17. U18 and U19 are clocked by the 300Hz oscillator
U22 to generate the VIS_PWR_CLK and the AUR_PWR_CLK
signals to drive the visual and aural up/down 12 bit counters.
Upon pressing an UP or DOWN button, U18 or U19 pin 23
PWR_CLK will issue one pulse then wait for 2 seconds and start
issuing a 300Hz clock rate if the button is still pressed.
IC U18 also generates a 9.5Hz clock used by the METER
CLOCK GATE U20 which operates similar to U18 & U19 but
at a slower one pulse per 1.17 second rate to clock U17 METER
SELECT 4 bit counter.
Oscillator U22 is running about 77.6kHz and is programmed for
a divide by 256 to produce the 300Hz output frequency.
4.3.8
BATTERY (BAT) SUPPLY VOLTAGE
All the PALs operate from the BAT Vcc supply line which
maintains voltage on the counters in the event of a power failure.
At some point after that all counters will be reset to 0 on power
return if BAT drops to a low enough voltage. BAT is supplied by
three AA size batteries mounted on the rear of the exciter.
4.3.9
Visual Power Control
The visual power control is shown on sheet 5 of the schematic
and controls the rf output of the visual channel. The 12 bit
up/down counter consists of U26 & U27 which supplies a binary
code to the DAC U25 which controls the gain of U24-1
VIS_DAC_BUF. The signal is passed through the rf mute switch
U23-1 to 2 and on to U23-3 to 4 CW LEVEL SET switch and on
to U24-5 VIS_CTRL_BUF subtractor circuit where the visual
reflected power foldback input reduces the output when applied.
VIS_PWR_CTRL J1-23 will normally swing between 0 and 4
volts for a 0 to 1 watt output level but can vary somewhat and
will depend on where R48 VIS_PWR_LIMIT is set.
4.3.10
Aural Power Control
The aural power control shown on sheet 6 of the schematic works
the same as the visual except there is no CW_LEVEL_SET
switch in the aural path.
4.3.11
Power Up Reset
The power up reset circuit is U31 which forms a voltage compa-
rator referenced to the 1.23 volts of CR11, normal power fail
detection point is about 4.6 volts. When the voltage of U31-3 is
more than U31-2 then U31-1 will assert a Hi removing the power
up reset signal.
4.3.12
JP2 & JP3
These two jumpers extend AUR_GROUP_DELAY and
NOTCH_DIP_ENABLE signals to the remote control interface.
4.3.13
FREQ UNLOCK
The unlocked status of the three phased locked oscillator is
displayed by DS27, DS28, & DS29 and passed to PAL U17
where they are combined to produce the signal FREQ_LOCK*
on U17-23. FREQ_LOCK* drives the FREQ UNLOCK status
indicator and the U27-11 where it is combined with
VIDEO_LOSS_DELAY* to generate RF_MUTE U27-22. Also
if any FREQ UNLOCK or VIDEO LOSS DELAY is asserted low
the exciter will mute the rf output.
Platinum™ Series
4-2 888-2457-001 Rev. B: 7/15/02
WARNING: Disconnect primary power prior to servicing.