GD32VF103 User Manual
442
SLPWMOD bit in CAN_CTL register will be cleared automatically.
0: The sleeping working mode is left manually by software
1: The sleeping working mode is left automatically by hardware
4
ARD
Automatic retransmission disable
0: Enable Automatic retransmission
1: Disable Automatic retransmission
3
RFOD
Receive FIFO overwrite disable
0: Enable receive FIFO overwrite when receive FIFO is full and overwrite the FIFO
with the incoming frame
1: Disable receive FIFO overwrite when receive FIFO is full and discard the
incoming frame
2
TFO
Transmit FIFO order
0: Order with the identifier of the frame
1: Order with first in and first out
1
SLPWMOD
Sleep working mode
If this bit is set by software, the CAN enter sleep working mode after current
transmission or reception complete. This bit can cleared by software or hardware.
If AWU bit in CAN_CTL register is set, this bit is cleared by hardware when CAN
bus activity detected.
0: Disable sleep working mode
1: Enable sleep working mode
0
IWMOD
Initial working mode
0: Disable initial working mode
1: Enable initial working mode
20.4.2.
Status register (CAN_STAT)
Address offset: 0x04
Reset value: 0x0000 0C02
This register has to be accessed by word(32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
RXL
LASTRX
RS
TS
Reserved
SLPIF
WUIF
ERRIF
SLPWS
IWS
r
r
r
r
rc_w1
rc_w1
rc_w1
r
r
Bits
Fields
Descriptions
31:12
Reserved
Must be kept at reset value