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PC104P-SIO4BX User Manual, Revision: 0

General Standards Corporation

8302A Whitesburg Drive Huntsville, AL 35802, Phone: (256) 880-8787

CHAPTER 5: HARDWARE CONFIGURATION

5.0

Board Layout

The following figure is a drawing of the physical components of the PC104P-SIO4BX:

o
n
n

Multi-

Protocol

Xcvr

Multi-

Protocol

Xcvr

Multi-

Protocol

Xcvr

Multi-

Protocol

Xcvr

Multi-

Protocol

Xcvr

Multi-

Protocol

Xcvr

Multi-

Protocol

Xcvr

Multi-

Protocol

Xcvr

R
P

1
0
4

R
P

1
0
1

R
P

1
0
3

R
P

1
0
2

-S

-M

. (

J2 (ISA) * not installed for PCI104

J3 (ISA) * not installed for PCI104

J1 (PCI)

PC104P-SIO4BX / PCI104-SIO4BX TOP

6
8

o
n
n

PCI Bridge

JP1

FPGA

U11

U12

PC104P-SIO4BX / PCI104-SIO4BX BOTTOM

Figure 5-1: Board Layout

Содержание PC104P-SIO4BX

Страница 1: ...WITH DEEP TRANSMIT AND RECEIVE FIFOS AND MULTIPROTOCOL TRANSCEIVERS RS 485 RS 422 V 11 RS 423 V 10 RS 232 V 28 General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8...

Страница 2: ...tion assumes no responsibility for any errors that may exist in this document No commitment is made to update or keep current the information contained in this document General Standards Corporation d...

Страница 3: ...Digital Interface Circuits EIA order number EIA RS 422A EIA 485 Standard for Electrical Characteristics of Generators and Receivers for Use in Balanced Digital Multipoint Systems EIA order number EIA...

Страница 4: ...UPT CONTROL LOCAL OFFSET 0X0060 9 2 1 10 2 INTERRUPT STATUS CLEAR LOCAL OFFSET 0X0064 9 2 1 10 3 INTERRUPT EDGE LEVEL INTERRUPT HI LO LOCAL OFFSET 0X0068 0X006C 9 2 1 11 CHANNEL PIN SOURCE LOCAL OFFSE...

Страница 5: ...0 0X94 23 CHAPTER 5 HARDWARE CONFIGURATION 24 5 0 BOARD LAYOUT 24 5 1 BOARD ID JUMPER JP1 25 5 2 PC104P PCI104 SLOT SELECT SWITCH U4 25 CHAPTER 6 ORDERING OPTIONS 27 6 0 ORDERING INFORMATION 27 6 1 IN...

Страница 6: ...nous Serial Data Rates up to 10 Mbps Asynchronous Serial Data Rates up to 1 25 Mbps Independent Transmit and Receive FIFOs for each Serial Channel Up to 32k Deep Each Serial Mode Protocols include Asy...

Страница 7: ...g Z16C30 Universal Serial Controllers provide the four serial data channels The Z16C30 USCs serve as serial parallel converters which can be software configured to provide a variety of serial protocol...

Страница 8: ...om board control functions while the USC Registers map the Zilog Z16C30 registers into local address space The register block for each USC channel is accessed at a unique address range The table below...

Страница 9: ...O 000000XX 0x004C D32 Read Write Ch 4 Control Status 0000CC00 0x0050 D32 Read Write Ch 1 Sync Byte 00000000 0x0054 D32 Read Write Ch 2 Sync Byte 00000000 0x0058 D32 Read Write Ch 3 Sync Byte 00000000...

Страница 10: ...nel Request allows the software to multiplex the DMA channels This is typically handled by the driver the end user should have no need to change this register D31 Board Reset 1 Reset all Local registe...

Страница 11: ...used to determine a fill level for a specific transfer size D31 16 Tx Almost Full Flag Value Almost Full Flag will be asserted when the FIFO has space for Almost Full Value words or fewer i e FIFO con...

Страница 12: ...Active Low 0 Tx Empty D7 0 Channel Control Bits D7 Reset USC Pulsed 1 Reset USC chip Notes This value will automatically clear to 0 Following a USC Reset the next access to the USC must be a write of...

Страница 13: ...Falling Edge IRQ19 Channel 1 Rx FIFO Full Rising Edge Falling Edge IRQ20 Channel 2 Tx FIFO Empty Rising Edge Falling Edge IRQ21 Channel 2 Tx FIFO Full Rising Edge Falling Edge IRQ22 Channel 2 Rx FIFO...

Страница 14: ...pt Status Clear Register will have no effect on the interrupt If the interrupt source is a level triggered interrupt USC interrupt the interrupt status may still be 1 even if the interrupt is disabled...

Страница 15: ...ransceiver control for further information D30 Termination Disable For RS422 RS485 and V 35 the RxC RxAuxC and RxD have built in termination at the transceivers These internal terminations may be disa...

Страница 16: ...D19 TxD Source 0 X USC_TxD 1 0 Output 0 1 1 Output 1 D18 17 Cable TxAuxC Output Control Defines the Clock Source for the TxAuxC signal to the IO connector D18 D17 TxD Source 0 0 Tristate 0 1 On board...

Страница 17: ...1 Output to IO Connector 1X Output D10 9 USC_CTS Direction Setup Defines the CTS direction for the USC CTS pin Notes If CTS is used as GPIO set this field to 00 and set Pin Source Register D14 D13 for...

Страница 18: ...y be used as either an input or output to the USC the clock source must agree with the USC Clock setup USC IO Control Reg D2 0 to ensure the signal is not being driven by both the USC and the FPGA D2...

Страница 19: ...Size Registers display the sizes of the installed data FIFOs This value is calculated at power up This value along with the FIFO Count Registers may be used to determine the amount of data which can...

Страница 20: ...initialize the BCR in the USC To complete the Reset process the user should write data 0x00 to USC base address offset 0x100 or 0x300 to correctly initialize the BCR Following this initial byte write...

Страница 21: ...gramming details please refer to the Zilog Z16C30 data books Channel Offset Address Access Register Name 0x01 0x00 CCAR Hi Lo Channel Command Address Register 0x03 0x02 CMR Hi Lo Channel Mode Register...

Страница 22: ...it of the USC Channel Command Address Register CCAR The FIFO resets allow each individual FIFO Tx and Rx to be reset independently Setting the FIFO reset bit will clear the FIFO immediately 3 2 FIFO A...

Страница 23: ...enough available FIFO space to complete the transfer If the transfer size is larger than the available data the transfer will complete with invalid results This is the preferred mode for DMA operatio...

Страница 24: ...ed as an output or input clock signal or as a general purpose IO configured by the Pin Source register See Section 2 1 11 for further information on the Pin Source register The USC Clocks USC_RxC and...

Страница 25: ...esent a problem since the USC only has two clock pins Since one clock is necessary for receive clock and the other is necessary for the transmit clock there is no clock pin available for an input to t...

Страница 26: ...gnal The DCD and AuxC direction is set in the Pin Source register fields independent of DCE DTE mode Signal DTE DCE DTE Ext Loopback DCE Ext Loopback TxC TxC Out RxC In TxC Out RxC In Unused RxC RxC I...

Страница 27: ...fect on the SIO4BX performance The following section attempts to filter the information from the PCI9080 manual to provide the necessary information for a SIO4BX specific driver The SIO4BX uses an on...

Страница 28: ...1 DMA are supported 4 1 4 1 DMA Channel Mode Register PCI 0x80 0x94 The DMA Channel Mode register must be setup to match the hardware implementation Bit Description Value Notes D1 0 Local Bus Width 1...

Страница 29: ...i Protocol Xcvr Multi Protocol Xcvr Multi Protocol Xcvr Multi Protocol Xcvr Multi Protocol Xcvr Multi Protocol Xcvr Multi Protocol Xcvr R P 1 0 4 R P 1 0 1 R P 1 0 3 R P 1 0 2 PC104P SIO4BX BASE REV N...

Страница 30: ...2 2 of the PC 104 Plus specification Version 1 2 The exact relationship or mapping of switch positions and slot specific signals may vary among manufacturers of PC104 Plus motherboards Switch Position...

Страница 31: ...46 RTS3 CTS3 RTS3 CTS3 RTS3 CTS3 13 TXD1 RXD1 Unused Unused 47 TXD3 RXD3 Unused Unused 14 TXD1 RXD1 TXD1 RXD1 TXD1 RXD1 48 TXD3 RXD3 TXD3 RXD3 TXD3 RXD3 15 TXC1 RXC1 Unused Unused 49 TXC3 RXC3 Unused...

Страница 32: ...ordered with a single connector to allow the user to adapt the other end for a specific application A standard cable is available which will breakout the serial channels into four DB25 connectors Shie...

Страница 33: ...C CLOCK RAM is accessed through 2 registers at local offset 0x00A0 Address Reg and 0x00A4 Data Reg The user simply sets the RAM Address register to the appropriate offset then reads or writes the the...

Страница 34: ...is not post divided A value of 2 will provide a post divide of 4 2 2 This will allow for a post divide value of up to 32768 2 15 for each input clock Bit D7 of the Control word qualifies writes to the...

Страница 35: ...Hi 0x00 0x17 OSC Setting 0x00 0x18 Reserved 0x00 0x19 Reserved 0x00 0x1A Reserved 0xE9 0x1B Reserved 0x08 0x1C 0x3F Reserved Unused 0x00 0x40 PLL1 Q Setup0 0x00 0x41 PLL1 P Lo 0 Setup0 0x00 0x41 PLL1...

Страница 36: ...PCI bus interface D28 1 64 bit PCI bus interface 0 32 bit PCI bus interface D27 D24 Form Factor 0 Reserved 1 PCI 2 PMC 3 cPCI 4 PC104P D23 D20 HW Board sub field of form factor 0 PC104P SIO4B 1 PC104P...

Страница 37: ...level 1 RS232 support Pin Source Change 2 Multi Protocol support 3 Common Internal External FIFO Support 4 FIFO Latched Underrun Overrun Level 5 Demand mode DMA Single Cycle for Tx 6 DMA_Single_Cycle...

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