PC104P-SIO4BX User Manual, Revision: 0
General Standards Corporation
8302A Whitesburg Drive Huntsville, AL 35802, Phone: (256) 880-8787
2.1.10.1
Interrupt Control: Local Offset 0x0060
The Interrupt Control register individually enables each interrupt source. A ‘1’ enables each interrupt source; a ‘0’
disables. An interrupt source must be enabled for an interrupt to be generated.
2.1.10.2
Interrupt Status/Clear: Local Offset 0x0064
The Interrupt Status Register shows the status of each respective interrupt source. If an interrupt source is enabled in
the Interrupt Control Register, a ‘1’ in the Interrupt Status Register indicates the respective interrupt has occurred.
The interrupt source will remain latched until the interrupt is cleared, either by writing to the Interrupt Status/Clear
Register with a ‘1’ in the respective interrupt bit position, or the interrupt is disabled in the Interrupt Control register.
If an interrupt source is not asserted or the interrupt is not enabled, writing a ‘1’ to that bit in the Interrupt
Status/Clear Register will have no effect on the interrupt.
If the interrupt source is a level triggered interrupt (USC interrupt), the interrupt status may still be ‘1’ even if the
interrupt is disabled. This indicates the interrupt condition is true, regardless of whether the interrupt is enabled.
Likewise, if a level interrupt is enabled and the interrupt source is true, the interrupt status will be reasserted
immediately after clearing the interrupt, and an additional interrupt will be requested.
2.1.10.3
Interrupt Edge/Level & Interrupt Hi/Lo: Local Offset 0x0068 / 0x006C
The Interrupt Edge/Level and Interrupt Hi/Lo Registers define each interrupt source as level hi, level lo, rising edge,
or falling edge. All SIO4BX interrupts are edge triggered except the USC interrupts which are level triggered.
Since the interrupt behavior is fixed, the Interrupt Edge/Level register cannot be changed by the user. (Read Only)
The FIFO Flags may be defined as rising edge or falling edge via the Interrupt Hi/Lo Register. For example, a rising
edge of the Tx Empty source will generate an interrupt when the Tx FIFO becomes empty. Defining the source as
falling edge will trigger an interrupt when the Tx FIFO becomes “NOT Empty”.
