General Standards Corporation PC104P-SIO4BX, Руководство пользователя по оборудованию

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PC104P-SIO4BX User Manual, Revision: 0
General Standards Corporation
8302A Whitesburg Drive Huntsville, AL 35802, Phone: (256) 880-8787
2.1.13 Programmable Clock Registers: Local Offset 0x00A0 / 0x00A4 / 0x00A8
The Programmable Clock Registers allow the user to program the on-board programmable oscillator and configure
the channel clock post-dividers. As GSC should provide software routines to program the clock, the user should
have no need to access these registers. See section 3.6 for more information.
2.1.14 FIFO Count Register: Local Offset 0x00D0 / 0x00D4 / 0x00D8 / 0x00DC
The FIFO Count Registers display the current number of words in each FIFO. This value, along with the FIFO Size
Registers, may be used to determine the amount of data which can be safely transferred without over-running (or
under-running) the FIFOs.
D31:D16 Number of words in Rx FIFO
D15:D0 Number of words in Tx FIFO
2.1.15 FIFO Size Register: Local Offset 0x00E0 / 0x00E4 / 0x00E8 / 0x00EC
The FIFO Size Registers display the sizes of the installed data FIFOs. This value is calculated at power-up This
value, along with the FIFO Count Registers, may be used to determine the amount of data which can be safely
transferred without over-running (or under-running) the FIFOs.
D31:D16 Size of installed Rx FIFO
D15:D0 Size of installed Tx FIFO
2.1.16 Features Register: Local Offset 0x00FC
The Features Register allows software to account for added features in the firmware versions. Bits will be assigned
as new features are added.
D31:16 RESERVED
D15:8 Features Rev Level
01 – RS232 support, update Pin Source
02 – Multiprotocol support
03 – Common Internal/External FIFO code
04 – Latched FIFO Overrun/Underrun Level
05 – Demand mode DMA Single Cycle for Tx
06 - Single Cycle DMA disable, update Pin Source TxAuxC
07 - Rx Underrun Only, Reset Status
08 - Clock to 50Hz with 10Hz resolution
09 - No Legacy Support (No Clock Control Register)
0A - Falling Int fix
D7 Demand Mode DMA Single Cycle Disable feature implemented
D6 Board Reset feature implemented
D5 FIFO Counters/Size implemented
D4
‘1’
D3:0 Programmable Clock Configuration
0x3 = CY22393 - 4 Oscillators (Sio4B/BX configuration)