PC104P-SIO4BX User Manual, Revision: 0
General Standards Corporation
8302A Whitesburg Drive Huntsville, AL 35802, Phone: (256) 880-8787
2.1.8 Channel Control/Status: Local Offset 0x001C / 0x002C / 0x003C / 0x004C
The Channel Control/Status Register provides the reset functions and data transceiver enable controls, and the FIFO
Flag status for each channel.
D31:16 RESERVED
D15:8 Channel Status Bits
D15
Channel Rx FIFO Full Flag Lo
(Active Low -- 0=Rx Full)
D14
Channel Rx FIFO Almost Full Flag Lo
(Active Low -- 0=Rx Almost Full)
D13
Channel Rx FIFO Almost Empty Flag Lo
(Active Low -- 0=Rx Almost Empty)
D12
Channel Rx FIFO Empty Flag Lo
(Active Low -- 0=Rx Empty)
D11
Channel Tx FIFO Full Flag Lo
(Active Low -- 0=Tx Full)
D10
Channel Tx FIFO Almost Full Flag Lo
(Active Low -- 0=Tx Almost Full)
D9
Channel Tx FIFO Almost Empty Flag Lo
(Active Low -- 0=Tx Almost Empty)
D8
Channel Tx FIFO Empty Flag Lo
(Active Low -- 0=Tx Empty)
D7:0 Channel Control Bits
D7
Reset USC (Pulsed)
‘1’ = Reset USC chip
Notes:
This value will automatically clear to ‘0’.
Following a USC Reset, the next access to the USC must be a write of 0x00 to Local
Offset 0x100 (Ch1/2) or Local Offset 0x300 (Ch3/4).
Since two channels share each USC (Ch1 & Ch2, Ch3 & Ch4), resetting a USC will
affect both channels.
D6:2
RESERVED
D1
Reset Channel Rx FIFO (Pulsed)
1 = Reset/Clear Channel Rx FIFOs.
Note:
This value will automatically clear to ‘0’.
D0
Reset Channel Tx FIFO (Pulsed)
1 = Reset/Clear Channel Tx FIFOs.
Note:
This value will automatically clear to ‘0’.
2.1.9 Channel Sync Detect Byte: Local Offset 0x0050 / 0x0054 / 0x0058 / 0x005C
The Sync Detect Byte allows an interrupt to be generated when the received data matches the Sync Detect Byte.
D31:8
RESERVED
D7:0
Channel Sync Detect Byte
If the data being loaded into the Receive FIFO matches this data byte, an interrupt
request (Channel Sync Detect IRQ) will be generated. The interrupt source must be
enabled in the Interrupt Control Register in order for an interrupt to be generated.
