PC104P-SIO4BX User Manual, Revision: 0
General Standards Corporation
8302A Whitesburg Drive Huntsville, AL 35802, Phone: (256) 880-8787
CHAPTER 3: PROGRAMMING
3.0
Introduction
This section addresses common programming questions when developing an application for the SIO4. General
Standards has developed software libraries to simplify application development. These libraries handle many of the
low-level issues described below, including Resets, FIFO programming, and DMA. These libraries may default the
board to a “standard” configuration (one used by most applications), but still provide low-level access so
applications may be customized. The following sections describe the hardware setup in detail for common
programming issues.
3.1
Resets
Each serial channel provides control for three unique reset sources: a USC Reset, a Transmit FIFO Reset, and a
Receive FIFO Reset. All three resets are controlled from the GSC Channel Control/Status Registers. In addition, a
Board Reset has been implemented in the Board Control Register. This board reset will reset all local registers to
their default state as well as reset all FIFOs and USCs (all channels will be reset).
Section 2.2.1
provides information on the USC Reset. It is important to realize that since each Zilog Z16C30 chip
contains two serial channels, a USC Reset to either channel will reset the entire chip (both channels affected). Due
to the limitation of a USC Reset to affecting two channels, it is recommended that a single USC Channel be Reset via
the RTReset bit of the USC Channel Command/Address Register (CCAR).
The FIFO resets allow each individual FIFO (Tx and Rx) to be reset independently. Setting the FIFO reset bit will
clear the FIFO immediately.
3.2
FIFO Almost Flags
The FIFO Almost Empty and Almost Full flags of the SIO4BX provide a way for the user to approximate the amount
of data in the FIFO. Since FIFO Count Registers are available to provide the exact number of words in each FIFO,
the FIFO Almost Flags are not needed in most applications. If RTS functionality is used (Section 3.9), the Rx
Almost Full Flag is used to set the RTS disable level. The FIFO Almost Flags may also be useful to provide an
interrupt at a specific FIFO fill level.
Each channel provides two 32 bit registers for setting the Almost Full/Empty values: the Tx FIFO Almost Register
(See Section 2.1.5) and the Rx FIFO Almost Register (See Section 2.1.6). Each of these registers is further divided
into two 16 bit words: D31-D16 = Almost Full Value; D15-D0 = Almost Empty Value.
The Almost Flag value represents the number of bytes from each respective “end” of the FIFO. The Almost Empty
value represents the number of bytes from empty, and the Almost Full value represents the number of bytes from full
(NOT the number of bytes from empty). For example, the default value of “0x0007 0007” in the FIFO Almost
Register means that the Almost Empty Flag will indicate when the FIFO holds 0x0007 bytes or fewer, and will
transition as the 8
th
byte is read or written. The Almost Full Flag indicates the FIFO contains (FIFO Size – 0x7)
bytes or more. For the standard 32Kbyte FIFO, an Almost Full value of 0x7 will cause the Almost Full flag to be
asserted when the FIFO contains 32761 (32k – 7) or more bytes of data .
