Index
IN-2
C141-E145-02EN
O
operation 6-1
operation, caching 6-12
operation, read-ahead 6-12
P
partial hit 6-18
pausing, device Ultra DMA data out burst
5-139
pausing, host Ultra DMA data in burst
5-134
PIO data transfer 5-127
timing 5-127
power commands 6-9
power-on 5-142
timing 5-142
power save 6-7
mode 6-7
processing, defect 6-9
processing, sector slip 6-10
R
read-ahead 6-12
cache 6-12
operation 6-12
READ DMA 6-13
reading, sequential 6-15
READ MULTIPLE 6-13
READ SECTOR(S) 6-13
reset 5-142, 6-2
reset response 6-20
reset timing 5-142
resistor, pull-up or pull-down 5-126
response, to
diagnostic command 6-6
hardware reset 6-3
power-on 6-2
software reset 6-5
response to
diagnostic command 6-6
hardware reset 6-3
power-on 6-2
software reset 6-5
S
sector slip processing 6-10
sequential command 6-15
sequential hit 6-16
sequential reading 6-15
sleep mode 6-8
spare area 6-9
standby mode 6-8
status report in event of error 6-20
sustain, Ultra DMA data
in burst 5-133
out burst 5-138
sustained Ultra DMA data
in burst 5-133
out burst 5-138
T
terminating, device Ultra DMA data out
burst 5-135, 5-141
terminating, host Ultra DMA data
in burst 5-136
out burst 5-140
timing, multiword DMA data transfer
5-128
timing, PIO data transfer 5-127
timing, power-on 5-142
timing, reset 5-142
timing requirement, Ultra DMA data burst
5-130
U
Ultra DMA data burst timing requirement
5-130
Ultra DMA data transfer 5-129
Ultra DMA recipient timing requirement
5-132
Ultra DMA sender timing requirement
5-132
using, read segment buffer 6-14
using read segment buffer 6-14
W
write cache 6-19
WRITE SECTOR (S) EXT (34H) 5-102
X
X'B1' 5-90
Содержание MHR2010AT
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Страница 58: ...Theory of Device Operation 4 6 C141 E145 02EN Figure 4 3 Circuit Configuration ...
Страница 188: ...Interface 5 114 C141 E145 02EN g d f f d e Figure 5 7 Normal DMA data transfer ...
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