75
3.1 Outline of Clock Generator and Controller
■
Clock Generator and Controller Block Diagram
Figure 3.1.2 is a block diagram of the clock generator and controller.
Figure 3.1-2 Block Diagram of the Clock Generator and Controller
X0
PLL
X1
1/2
R
|
B
U
S
[Gear controller]
GCR register
CPU gear
Peripheral
gear
PCTR register
Oscilla-
tion
circuit
Selector circuit
Internal
clock
generation
circuit
CPU clock
Internal bus clock
External bus clock
Peripheral
DMA clock
Internal peripheral
clock
[Stop/sleep controller]
Internal interrupt
Internal reset
STCR register
CPU hold permission
Status
transition
control
circuit
Stop state
Sleep state
CPU hold request
Internal reset
Reset
generation
F/F
[DMA suppression
circuit]
DMA request
PDRR register
[Reset reason circuit]
Power-on reset
RSTX pin
RSRR register
[Watchdog controller]
WPR register
Watchdog F/F
CTBR register
Timebase timer
Count clock
Содержание MB91F109
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Страница 95: ...71 2 10 Operation Mode MODR writing RSTX reset MD2 1 0 BW1 and BW0 of AMD0 to AMD5 Bus width specification ...
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Страница 224: ...200 CHAPTER 4 BUS INTERFACE ...
Страница 234: ...210 CHAPTER 5 I O PORTS ...
Страница 268: ...244 CHAPTER 9 U TIMER ...
Страница 290: ...266 CHAPTER 10 UART ...
Страница 314: ...290 CHAPTER 12 16 BIT RELOAD TIMER ...
Страница 322: ...298 CHAPTER 13 BIT SEARCH MODULE ...
Страница 392: ...368 CHAPTER 16 FLASH MEMORY ...
Страница 432: ...408 APPENDIX E Instructions F Table E 2 Instruction Formats OP rel11 5 11 ...
Страница 448: ...424 APPENDIX E Instructions ...
Страница 449: ...425 INDEX INDEX The index follows on the next page This is listed in alphabetic order ...
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