Fujitsu MB90460 Series, Руководство по оборудованию, Страница: 240 / 739

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CHAPTER 11 WATCHDOG TIMER
11.2 Configuration of the Watchdog Timer
The watchdog timer consists of the following five blocks:
• Count clock selector
• Watchdog counter (2-bit counter)
• Watchdog reset generator
• Counter clear control circuit
• Watchdog timer control register (WDTC)
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Block Diagram of the Watchdog Timer
Figure 11.2-1 shows the block diagram of the watchdog timer.
Figure 11.2-1 Block diagram of the watchdog timer
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Count clock selector
This circuit is used to select the count clock of the watchdog timer from four types of time-base timer
outputs. This determines the watchdog reset generation time.
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Watchdog counter (2-bit counter)
This 2-bit up counter uses the time-base timer output as the count clock.
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Watchdog reset generator
Used to generate the reset signal by an overflow of the watchdog counter.
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Counter clear circuit
Used to clear the watchdog counter and to control the operation or stopping of the counter.
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Watchdog timer control register (WDTC)
Used to activate or clear the watchdog timer; holds the reset generation cause.
W a tchdog timer control regi s ter (WDTC)
W a tchdog timer
S t a rt of s leep mode
S t a rt of hold s t a t us mode
S t a rt of s top mode
Co u nter
cle a r control
circ u it
Co u nt
clock
s elector
Activ a tion
2- b it
Over-
W a tchdog
To the intern a l
with CLR
co u nter
re s et gener a tor
re s et gener a tor
flow
Cle a r
(Time- bas e timer co u nter)
One-h a lf of HCLK
HCLK: O s cill a tion clock