Freescale Semiconductor
MCIMX53SMD Board Hardware User’s Guide, Rev. 0
41
Figure 5-4.
Clock Source Locations (Bottom)
5.3.4
i.MX53 Internal Regulators
The i.MX53 Applications Processor contains two internal voltage regulators which can supply VDDA, VDDAL,
VDD_DIG_PLL, and VDD_ANA_PLL. The power input for this pin is VDD_REG (pin G18). On the MCIMX53SMD
board, this pin is connected to VBUCKPERI and is set to 2.5V.
The Digital PLL voltage regulator can be selected to supply VDD_DIG_PLL through an internal (on die)
connection. The VDD_DIG_PLL pin can also be connected to the VDDA and VDDAL pins through an external
connection to allow the Digital PLL regulator to supply these rails as well. The Digital PLL regulator is set to
start at a reduced voltage value of 1.2V, but is programmed by software to increase to 1.3V in the beginning of
the boot process. On the MCIMX53SMD board, the VDD_DIG_PLL connection to VLDO2 is not populated by
default, so that VDD_DIG_PLL power is supplied by the internal regulator. The VDDA supply pins are
connected to VLDO10 through a shorting trace SH22. If the developer wishes to experiment with supplying
VDDA from the internal regulator, the trace between the two pads of SH22 can be cut. The VDDAL supply pin
is connected to VLDO6 through a shorting trace SH24. If the developer wishes to experiment with supplying
VDDAL from the internal regulator, the trace between the two pads of SH24 can be cut.
The Analog PLL voltage regulator can be selected to supply VDD_ANA_PLL through an internal (on die)
connection. The Analog PLL is set to supply a voltage of 1.8V. On the MCIMX53SMD board, the VDD_ANA_PLL
connection to VLDO8 is not populated by default, so that VDD_ANA_PLL is supplied by the internal regulator.
NOTE
Developers should note that during the boot process, VDD_DIG_PLL takes ~ 310 ms to change
from 1.2V to 1.3V. During this time, the i.MX53 core will not run at full speed/maximum
processor loading, rather it will operate in the reduced power mode, with some limitations.
The limitations of the reduced power mode are discussed in the i.MX53 data sheet. It is
expected that during the first 310 ms, processor loading will not be an issue.
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