Freescale Semiconductor MCIMX53SMD, Руководство пользователя по оборудованию

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MCIMX53SMD Board Hardware User’s Guide, Rev. 0
Freescale Semiconductor
3. Specifications
3.1. i.MX53 Applications Processor
The i.MX53 processor is based on ARM Cortex-A8
TM
Platform, which has the following features:
MMU, L1 Instruction and L1 Data Cache
Unified L2 cache
Target frequency of the core (including Neon, VFPv3, and L1 Cache) is 1-1.2 GHz; target frequency of
the MCIMX53SMD platform is 1 GHz
Neon coprocessor (SIMD Media Processing Architecture) and Vector Floating Point (VFP-Lite)
coprocessor supporting VFPv3
TrustZone
The memory system of the processor consists of the following components:
Level 1 Cache:
o
Instruction (32 Kbyte)
o
Data (32 Kbyte)
Level 2 Cache:
o
Unified instruction and data (256 Kbyte)
Level 2 (internal) memory:
o
Boot ROM, including HAB (64 Kbyte)
o
Internal multimedia/shared, fast access RAM (128 Kbyte)
o
Secure/non-secure RAM (16 Kbyte)
External memory interfaces:
o
16/32-bit DDR2-800, LV-DDR2-800 or DDR3-800 up to 2 Gbyte
o
32 bit LPDDR2
o
8/16-bit NAND SLC/MLC Flash, up to 66 MHz, 4/8/14/16-bit ECC
o
16-bit NOR Flash. All WEIMv2 pins are muxed on other interfaces (data with NFC pins). I/O
muxing logic selects WEIMv2 port, as primary muxing at system boot.
o
16-bit SRAM, cellular RAM
o
Samsung One NANDTM and managed NAND including eMMC up to rev 4.4 (in muxed I/O
mode)
The i.MX53 processor system is built around the following system-on-chip (SoC) interfaces:
64-bit AMBA AXI v1.0 bus: Used by ARM platform, multimedia accelerators (such as, VPU, IPU, GPU3D,
GPU2D) and the external memory controller (EXTMC) operating at 200 MHz.
32-bit AMBA AHB 2.0 bus: Used by the rest of the bus master peripherals operating at 133 MHz.
32-bit IP bus: Peripheral bus used for control (and slow data traffic) of the most system peripheral
devices operating at 66 MHz.
The i.MX53 processor makes use of dedicated hardware accelerators to achieve state-of-the-art multimedia
performance. The use of hardware accelerators provides both high performance and low power consumption
while freeing up the CPU core for other tasks.
The i.MX53 processor incorporates the following hardware accelerators:
VPU, version 3: Video processing unit
GPU3D: 3D graphics processing unit, OpenGL ES 2.0, version 3, 33 Htri/s, 200 Mpix/s, and 800 Mpix/s
z-plane performance, 256 KB RAM memory.
GPU2D: 2D graphics accelerator, OpenVG 1.1, version 1, 200 Mpix/s performance.
IPU, version 3M: Image processing unit