Freescale Semiconductor
MCIMX53SMD Board Hardware User’s Guide, Rev. 0
39
When the MCIMX53SMD board was originally designed, several of the BOOT_CFG pins were selectable by the
two 8-position DIP Switch (SW26, SW28). After initial testing of the MCIMX53SMD board, the optimum
BOOT_CFG settings for flexibility and ease of use were determined. These are the default settings on the
board, which set the eMMC4.4 (eSDHC3) as the default boot source. As the developer becomes more familiar
with the board and wishes to experiment more, the next step for the developer is to write code for other
device to initialize it as alternative boot source and pass the boot process to the new source.
Figures 5-2
shows the location of BOOT Switch. The ON state indicates high (Power) logic level and the OFF
state indicates low (GND) logic level.
Figure 5-2.
Boot Switch (SW26, SW28)
5.3.3
Clock Signals
The i.MX53 processor uses three external clocks: Y1, Y3, and QZ3. The 24 MHz crystal (Y1) is the main clock
source for the processor. The crystal is located on the bottom side of the board as shown in
Figure 5-3
. It is
driven by its own 2.5V supply pin, NVCC_XTAL. Although the crystal frequency for the board is set to be 24
MHz, the default BOOT_CFG2[2] pin that controls the frequency is left to auto detect. In the case of 24 MHz,
the actual setting is not important. If a clock oscillator is used, it would be connected to the pin EXTAL (AB11),
and the pin XTAL (AC11) would be left floating. The 24 MHz clock signal can be outputted from any GPIO pin
for being used in other locations. On the MCIMX53SMD board, the clock signal is outputted from the GPIO_0
pin and the net is labeled GPIO_0(CLK0). The clock signal is sent to the Audio Codec as the clock source for the
audio sub-system, and it is also sent to the expansion port as an available clock signal for a custom designed
card, if needed.
The 22.5792MHz OSC(Y3) is the clock source used by the i.MX53 processor and Audio Codec for high
performance. It receives power from the VLDO8 1.8V voltage regulator and can be shut by GPIO
OSC_CKIH1_EN. The location of the crystal is also shown in
Figure 5-3
.
SW26, SW28
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