Freescale Semiconductor 56F8300 Series, Руководство пользователя

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56F8357EVM User Manual, Rev. 1
2-4 Freescale Semiconductor
Preliminary
2.2 Program and Data Memory
The 56F8357EVM contains two 128K x 16-bit Fast Static RAM banks. SRAM bank 0 is
controlled by CS0 and SRAM bank 1 is controlled by CS1 and CS4. This provides a total of
256K x 16 bits of external memory.
2.2.1 SRAM Bank 0
SRAM bank 0, which is controlled by CS0, uses a 128K
×
16-bit Fast Static RAM (GSI GS72116,
labeled U2) for external memory expansion; see the FSRAM schematic diagram in Figure 2-1 .
CS0 can be configured to use this memory bank as 16 bits of Program memory, Data memory, or
both. Additionally, CS0 can be configured to assign this memory’s size and starting address to
any modulo address space.
This memory bank will operate with zero Wait State access while the MC56F8357 is running at
60MHz and can be disabled by removing the jumper at JG7.
Figure 2-1. Schematic Diagram of the External CS0 Memory Interface
2.2.2 SRAM Bank 1
SRAM bank 1, which is controlled by CS1 and CS2, uses a 128K
×
16-bit Fast Static RAM (GSI
GS72116, labeled U3) for external memory expansion; see the FSRAM schematic diagram in
Figure 2-2 . Using CS1 and CS4, this memory bank can be configured as byte (8-bit) or word
(16-bit) accessable Program memory, Data memory, or both. Additionally, CS1 and CS4 can be
configured to assign this memory’s size and starting address to any modulo address space.
56F8357
GS72116
A0-A16
D0-D15
RD
WR
A0-A16
DQ0-DQ15
OE
WE
CE
1 2
JG7
+3.3V
Jumper Pin 1-2:
Enable SRAM
PS/CS0
Jumper Removed:
Disable SRAM