Freescale Semiconductor 56F8300 Series, Руководство пользователя

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Preface
Freescale Semiconductor ix
Preliminary
56F8357
Hybrid controller with motor control peripherals
EOnCE
Enhanced On-Chip Emulation; a debug bus and port was created to
enable a designer to create a low-cost hardware interface for a
professional-quality debug environment
EVM
Evaluation Module; a hardware platform which allows a customer to
evaluate the silicon and develop his application
FlexCAN
Flexable CAN Interface Module; a peripheral on the 56F8357 part
GPIO
General Purpose Input and Output port on Freescale’s family of hybrid
controllers; does not share pin functionality with any other peripheral on
the chip and can only be set as an input, output or level-sensitive
interrupt input
IC
Integrated Circuit
JTAG
Joint Test Action Group; a bus protocol/interface used for test and debug
LED
Light Emitting Diode
LQFP Low-profile Quad Flat Package
MPIO
Multi-Purpose Input and Output port on Freescale’s family of hybrid
controllers; shares package pins with other peripherals on the chip and
can function as a GPIO
OnCE
TM
On-Chip Emulation, a debug bus and port created to allow a means for
low-cost hardware to provide a professional-quality debug environment
PCB
Printed Circuit Board
PLL
Phase Locked Loop
PWM
Pulse Width Modulation
QuadDec
Quadrature Decoder; a peripheral on the 56F8357 part
RAM
Random Access Memory
R/C
Resistor/Capacitor Network
ROM
Read-Only Memory
SCI
Serial Communications Interface; a peripherial on Freescale’s family of
hybrid controllers
SPI
Serial Peripheral Interface; a peripheral on Freescale’s family of hybrid
controllers
SRAM
Static Random Access Memory
UART Universal Asynchronous Receiver/Transmitter
WS
Wait State