Debug Support
Technical Summary, Rev. 1
Freescale Semiconductor
2-11
Preliminary
2.7.1 JTAG Connector
The JTAG connector on the 56F8357EVM allows the connection of an external Host Target
Interface for downloading programs and working with the 56F8357’s registers. This connector is
used to communicate with an external Host Target Interface, which passes information and data
back and forth with a host processor running a debugger program.
Table 2-7
shows the pin-out
for this connector.
When this connector is used with an external Host Target Interface, the parallel JTAG interface
should be disabled by placing a jumper in jumper block JG3. Reference
Table 2-8
for this
jumper’s selection options.
Table 2-7. JTAG Connector Description
J3
Pin #
Signal
Pin #
Signal
1
TDI
2
GND
3
TDO
4
GND
5
TCK
6
GND
7
NC
8
KEY
9
RESET
10
TMS
11
+3.3V
12
NC
13
DE
14
TRST
Table 2-8. Parallel JTAG Interface Disable Jumper Selection
JG3
Comment
No jumpers
Enables On-board Parallel JTAG Interface
1–2
Disables on-board Parallel JTAG Interface
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