Program and Data Memory
Technical Summary, Rev. 1
Freescale Semiconductor
2-5
Preliminary
This memory bank will operate with zero Wait State access while the 56F8357 is running at
60MHz and can be disabled by removing the jumpers at JG8.
Figure 2-2. Schematic Diagram of the External CS1/CS4 Memory Interface
56F8357
GS72116
A0-A16
D0-D15
RD
WR
A0-A16
DQ0-DQ15
OE
WE
CE
JG8
Jumper Pin 1-2:
Enable SRAM Low Byte
DS/CS1
PD2/CS4
1
3
2
4
LB
HB
Jumper Pin 3-4:
Enable SRAM High Byte
Содержание 56F8300 Series
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