Formosa Industrial Computing MBM-530NS, Руководство пользователя

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-56- MBM-530NS User’s Manual
Name Description Name Description
SD0-SD15
[Input/Output]
System Data bit 0 to 15
AEN
[out put] The DMA Address Enable is
high when the DMA controller
is driving the address bus. It is
low when the CPU is driving
the address bus
BALE
[Output] The Buffered Address Latch
Enable is used to latch SA0 -
SA19 onto the falling edge.
This signal is forced high
during DMA cycles
-REFRESH
[Input/Output]
This signal is used to indicate a
memory refresh cycle and can
be driven by the
microprocessor on the I/O
channel
-IOCHCK
[Input]
The I/O Channel Check is an
active low signal which
indicates that a parity error
exist on the I/O board
TC
[Output] Terminal Count provides a
pulse when the terminal count
for any DMA channel is
reached
IOCHRDY
[Input, Open
collector]
This signal lengthens the I/O,
or memory read/write cycle,
and should be held low with a
valid address
SBHE
[Input/Output]
The System Bus High Enable
indicates the high byte SD8 -
SD15 on the data bus
IRQ 3-7, 9-12,
14, 15
[Input]
The Interrupt Request signal
indicates I/O service request
attention. They are prioritized
in the following sequence :
(Highest) IRQ 9, 10, 11, 12,
13, 15, 3, 4, 5, 6, 7 (Lowest)
-MASTER
[Input]
The MASTER is the signal
from the I/O processor which
gains control as the master
and should be held low for a
maximum of 15 microseconds
or system memory may be lost
due to the lack of refresh
-IOR
[Input/Output]
The I/O Read signal is an
active low signal which
instructs the I/O device to drive
its data onto the data bus
-MEMCS16
[Input, Open
collector]
The Memory Chip Select 16
indicates that the present data
transfer is a 1-wait state, 16-bit
data memory operation
-IOW
[Input/Output]
The I/O write signal is an active
low signal which instructs the
I/O device to read data from
the data bus
-IOCS16
[Input, Open
collector]
The I/O Chip Select 16
indicates that the present data
transfer is a 1-wait state, 16-bit
data I/O operation
-SMEMR
[Output]
The System Memory Read is
low while any of the low 1
mega bytes of memory are
being used
OSC
[Output] The Oscillator is a 14.31818
MHz signal used for the color
graphic card
-MEMR
[Input/Output]
The Memory Read signal is
low while any memory location
is being read
-ZWS
[Input, Open
collector]
The Zero Wait State indicates
to the microprocessor that the
present bus cycle can be
completed without inserting
additional wait cycle