Formosa Industrial Computing MBM-530NS, Руководство пользователя

Страница: 55 / 104

Web site: www.formosa21.com
MBM-530NS User’s Manual -55-
CN6 & CN7: PC-104 Connector
Name Description Name Description
BUSCLK
[Output]
The BUSCLK signal of the I/O
channel is asynchronous to the
CPU clock.
-SMEMW
[Output]
The System Memory Write is
low while any of the low 1
mega bytes of memory is being
written
RSTDRV
[Output]
This signal goes high during
power-up, low line-voltage or
hardware reset
-MEMW
[Input/Output]
The Memory Write signal is low
while any memory location is
being written
SA0 - SA19
[Input/Output]
The System Address lines run
from bit 0 to 19. They are
latched onto the falling edge of
"BALE"
DRQ 0-3, 5-7
[Input]
DMA Request channels 0 to 3
are for 8-bit data transfers.
DMA Request channels 5 to 7
are for 16-bit data transfers.
DMA request should be held
high until the corresponding
DMA has been completed.
DMA request priority is in the
following sequence:(Highest)
DRQ 0, 1, 2, 3, 5, 6, 7 (Lowest)
LA17- LA23
[Input/Output]
The Unlatched Address line
run from bit 17 to 23
-DACK 0-3,
5-7
[Output]
The DMA Acknowledges 0 to
3, 5 to 7 are the corresponding
acknowledge signals for DRQ
0 to 3 and 5 to 7
8 7 6 5 4 3 2 1
ON
MBM
-530
CN6
CN7