CPC522
CPCCPC522 User Manual
21
©2022 Fastwel Ver.001
Counter/Timer
As in PC/AT, the module is equipped with three 8254 type counters/timers integrated into the PCH.
Additional timer
The PCH includes an additional programmable timer that prevents the system from locking up
during startup. The first timer overflow generates an SMI# signal that causes a subroutine to exit
the software system hanging. If the timer overflows for the second time, a system reset signal is
generated to get the system out of the hardware hanging.
Watchdog Timer
The watchdog is designed to eliminate system blocking, both at startup and during operation.
When the watchdog is triggered a Reset, interrupt or SMI signal is generated. The actuation time is
set via the BIOS Setup menu. The watchdog monitors the execution of the BIOS code at system
startup.
The watchdog is implemented in the FPGA as an LPC bus device. The timer consists of a 24-bit
counter register [Timer Current Value Register], decremented at 32.768 kHz, and an initial value
register [Timer Initial Value Register]. When the counter register is zeroed, either an interrupt, an
NMI, or an automatic reset of the board can be generated. The actuation times can be set within
the range from 0 to 512 seconds inclusively, in increments of
30.52 µs.
By default, without pre-initialization the watchdog operate delay time is set to the maximum of 512
seconds. Below you can see the formula for calculating the T
WD
delay time (µs) depending on the
decimal value in the Timer Initial Value Register (K
WD
):
T
WD
[
µ
s
] = K
WD
* 10
6
/ 2
15
For example, the decimal value K
WD
= 1 (000001h) corresponds to a 30.52µs delay time, and
K
WD
= 16777215 (FFFFFFh) corresponds to a delay time of 512 seconds.
The counter can be reset to its initial value in several ways:
● By writing any number to the [Timer Current Value Register]
● By writing any number to port 80h (the mode is enabled in the [Timer Init Register])
By writing or reading from addresses in two windows (the base addresses of the windows are
specified in the corresponding registers [Window Base Address], the address mask is specified in
the [Windows 1&2 Address mask register], the mode is selected in the [Timer Init Register]). The
size of the windows is 1 to 16 bytes depending on the value of the mask in the register.
Accessing the watchdog timers
The configuration of the device is based on a Plug-and-Play architecture. The watchdog
registers can be accessed via the standard I/O registers (index and data) when entering the
configuration mode.
