CPC505
C P C 5 0 5 U s e r M a n u a l
39
© 2 0 2 2 F a s t w e l v . 0 0 1
Base+5
R/W
00h
RIO GPIO Direction
[7:0]
– GPIO Direction
0
– input
1
– output
Base+6
R/W
00h
RIO GPIO DATA
[7:0]
– GPIO DATA
Base+7
R/W
00h
User LEDs control
[7:2]
– Reserved
[2]
– RIO LED On/Off
[1]
– GREEN LED On/Off
[0]
– RED LED On/off
The controller automatically generates a sequence of access to the FRAM memory on the SPI bus
(address from registers BASE+0, BASE+1, read/write mode and data - register BASE+2).
The last kilobyte of 32 KB is reserved to save the BIOS Setup settings. Bit <0> in the control
register (Base + 3) enables automatic address increment mode when reading/writing the register of
data (base + 2), after the end of the batch exchange it must be reset.
3.4.2 Programming SPI device
The work with FRAM is in the I/O area by addresses 310h-313h.
▪ Write the data byte (32h) to FRAM by the address (144h)
MOV DX, 310H
MOV AL, 44H
OUT DX, AL
MOV DX, 311H
MOV AL, 01H
OUT DX, AL
MOV DX, 312h
MOV AL, 32h
OUT DX,AL
▪ Reading data byte from FRAM by the address (101h)
MOV DX, 310H
MOV AL, 01H
OUT DX, AL
MOV DX, 311H
MOV AL, 10H
OUT DX, AL
MOV DX, 312h
IN AL,DX
▪ Reading a batch of three bytes of FRAM data starting from the address 208h
MOV DX, 310H
MOV AL, 08H
OUT DX, AL