Fastwel CPC505, Руководство пользователя, Страница: 38 / 87

CPC505
C P C 5 0 5 U s e r M a n u a l
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© 2 0 2 2 F a s t w e l v . 0 0 1
2 STF Write/Read:
Second timeout flag. The flag is to
“1” if TMF=1. An interrupt occurs
on this flag. If the board reset is enabled RSTE=1, a hardware reset
occurs. It is reset by writing
“1” to this digit.
1 - Reserved
0 TMF Write/Read:
Timeout Flag. It is set to
“1” when the timer counter is zeroed. This
flag causes an interrupt to occur. Reset by writing
“1” to this bit or
writing to port 80h (if this mode is enabled).
Control Register
Base+7h
Bit Name Description
7:2 - Reserved
1
CNTE Write/Read:
Counter decrement
1
– enabled
0
– disabled
0 RSTE Write/Read:
Board reset by timeout
1
– reset is enabled
0
– reset is disabled
3.4 SPI/LEDs/GPIO controller
3.4.1 Description of the SPI controller registers
Table 3-16
– Registers of SPI controller
I/O port
address
Type HARD RESET Configuration register
Base+0 R/W 00h FRAM address value [7:0]
Base+1 R/W 00h FRAM address value [14:8]
Base+2 R/W 00h SPI data value [7:0]
Base+3 R/W 00h SPI Control/Status register
[7]
– busy status
[6]
– last 1K fram lock status
[5]
– Reserved
[4] - Reserved
[3]
– Reserved
[2]
– Reserved
[1]
– Reserved
[0]
– BURST mode
Base+4 R/W 00h Reserved