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CPC505
C P C 5 0 5 U s e r M a n u a l
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PCI
The PCI bus is implemented on a Pericom PI7C9X130 reversible bridge connected to the PCIe x4
bus. The following operating modes are supported: PCI 32bit/33MHz, PCI 64bit/66MHz. Both
system and peripheral slots are supported.
SPI
The interface is implemented in FPGA on the LPC bus. The FRAM chip (located on the board) is
supported. The maximum clock frequency is 25 MHz.
Audio
Support can be implemented through an RIO or an XMC module.
COM port
The COM0 port with RS-232 signal levels is routed to the connector (IDC2-10) on the printed
circuit board.
LED indication
Diagnostic LEDs for startup, drive activity, and user activity are on the front panel. Diagnostic LED
allows to distinguish 4 states of the board: power off, power on, BIOS startup, BIOS shutdown (OS
startup). Drives activity indicator informs about the activity of SATA interfaces. Two programmable
LEDs are for user's needs.
Watchdog
Hardware reset timer is implemented in FPGA on LPC bus.
Power supply reset and monitoring
The microprocessor reset signal is generated from the following sources:
• From supervisor at power on
• From Reset button
• From watchdog timer
• From Reset# signal of PCI bus (in the Slave mode).
Switches
(
Jumpers)
There is a reset switch to default BIOS settings on the board.