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BD500 Broadcast Profanity Delay
Appendix F Diagnostics
Page 35
©Eventide Inc. 1995-1999
doc release 10
Error Codes
A04
The 1st memory test program was uploaded to the copro-
cessor successfully and then run. This error message
indicates that the test program failed to make it to the first
marker. This means that the coprocessor test program
crashed. This does not indicate a memory failure although
there may be a short between memory select lines and
processor control lines.
A05
The 1st memory test program was uploaded to the copro-
cessor successfully and then run. This error message
indicates that the test program failed to make it to the sec-
ond marker (end of write phase). This means that the
coprocessor test program crashed. This does not indi-
cate a memory failure although there may be a short be-
tween memory select lines and processor control lines.
A06
The 1st memory test program was uploaded to the copro-
cessor successfully and then run. This error message
indicates that the test program failed to make it to the sec-
ond marker (end of read phase). This means that the co-
processor test program crashed. This does not indicate a
memory failure although there may be a short between
memory select lines and processor control lines.
A07
During the first coprocessor memory test an error was
found by the memory test but the reported error code does
not match one in the motherboard CPU's program.
A08
Error found by the 1st coprocessor external memory test.
The error appears to be a static memory error found dur-
ing the write cycle, i.e. a particular location didn't hold a
data word for several instruction times. This could be a
missing or badly soldered chip or a bad address or data
line.
A09
Error found by the 1st coprocessor external memory test.
The error appears to be a dynamic memory error found
during the write cycle, i.e. a particular location didn't hold
a data word for several instruction times. A09 was using
X basepage access. A10 was using P basepage access,
A11 was using Y banked page access. X basepage ac-
cess is first. If A09 occurs then the DRAM may be totally
dead or poorly socketed.
A10
Error found by the 1st coprocessor external memory test.
The error appears to be a dynamic memory error found
during the write cycle, i.e. a particular location didn't hold
a data word for several instruction times. A09 was using
X basepage access. A10 was using P basepage access,
A11 was using Y banked page access. X basepage ac-
cess is first. If A09 occurs then the DRAM may be totally
dead or poorly socketed.
A11
Error found by the 1st coprocessor external memory test.
The error appears to be a dynamic memory error found
during the write cycle, i.e. a particular location didn't hold
a data word for several instruction times. A09 was using
X basepage access. A10 was using P basepage access,
A11 was using Y banked page access. X basepage ac-
cess is first. If A09 occurs then the DRAM may be totally
dead or poorly socketed.
A12
Error found by the 1st coprocessor external memory test.
The error appears to be a static memory error found dur-
ing the read cycle, i.e. the memory was changed by some
later address write or other failure.
A13
Error found by the 1st coprocessor external memory test.
The test reports that a memory failure was found during
the first read back cycle. The error was detected when
the dynamic RAM was accessed using the X select line.
A14
Error found by the 1st coprocessor external memory test.
The test reports that a memory failure was found during
the first read back cycle. The error was detected when
the dynamic RAM was accessed using the P select line.
A15
Error found by the 1st coprocessor external memory test.
The test reports that a memory failure was found during
the first read back cycle. The error was detected when
the dynamic RAM was accessed using the Y select line.
A16
Error found by the 1st coprocessor external memory test.
During the 2nd read back of coprocessor external static
RAM an error was found.
A17
Error found by the 1st coprocessor external memory test.
The test reports that a memory failure occurred that is
related to a failure in the refresh circuitry. The error was
detected when the dynamic RAM was accessed using the
X select line.
A18
Error found by the 1st coprocessor external memory test.
The test reports that a memory failure occurred that is
related to a failure in the refresh circuitry. The error was
detected when the dynamic RAM was accessed using the
P select line.
A19
Error found by the 1st coprocessor external memory test.
The test reports that a memory failure occurred that is
related to a failure in the refresh circuitry. The error was
detected when the dynamic RAM was accessed using the
Y select line.
A21
During start-up (after the coprocessor is already known
to be working) a failure was reported by the motherboard
processor where it appears the coprocessor failed to re-
ceive a word of information from the motherboard. The
motherboard processor eventually got tired of waiting. This
is most likely caused by a software crash on the copro-
cessor. The crash may have been caused by intermittent
hardware.
A22
Similar to A21, this error indicates that the motherboard
processor was waiting for the coprocessor to transmit a
word of information to the motherboard when it gave up
waiting and generated this error message.
A30
During start-up a firmware error on the motherboard pro-
cessor occurred. The specific error is that sethostwrite-
ptr, part of the motherboard to coprocessor transmit driver
suite, was called with bad parameters. This looks like a
programming bug but might (unlikely) have been caused
by a hardware problem on the motherboard.
A32
During start-up the motherboard processor determined
that we arrived at a programming instruction waiting for
the coprocessor to finish processing a data word trans-
mission previously issued by the motherboard. We
shouldn't get here because the previous process that
would have issued that hardware interrupt would not have
exited without the dataword transmission being cleared.
This means that the coprocessor trashed it's own incom-
ing data bits (TxRDY/TxEMPTY) without the motherboard
CPU initiating it, or that the motherboard program has a
bug and somehow got out of the transmit function without
waiting for the data bits to be clear.
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Страница 16: ...Page 12 Chapter 2 Operation BD500 Broadcast Profanity Delay Eventide Inc 1995 1999 doc release 10 ...
Страница 22: ...Page 18 Chapter 3 Configuration BD500 Broadcast Profanity Delay Eventide Inc 1995 1999 doc release 10 ...
Страница 26: ...Page 22 Appendix B Basic Remote Control BD500 Broadcast Profanity Delay Eventide Inc 1995 1999 doc release 10 ...
Страница 50: ...Page 46 Appendix G Specifications BD500 Broadcast Profanity Delay Eventide Inc 1995 1999 doc release 10 ...