CMOS Setup Utility
SDRAM CAS Latency Time
When synchronous DRAM is installed, the number of clock cycles of CAS latency
depends on the DRAM timing.
The optional are: 3
(Default)
, 2
SDRAM Cycle Time Tras/Trc
Select the number of SCLKs for an access.
The optional are:
6/8 (Default)
, 5/7
This item allows you to configure the system based on the specific features of
the chipset. This chipset manages bus speed and access to system memory
recources, and external cache. It must be stated that these items should never
need to be altered.The default settings have been chosen because they provide
you the best operating conditions for your system. The only time you might
consider making any changes if you discovered that the datas were being lost
while control your system.
Advanced Chipset Features
Advanced Chipset Features
Advanced Chipset Features
Advanced Chipset Features
Advanced Chipset Features
CMOS Setup Utility - Copyright (C) 1984-2000 Award Software
Advanced Chipset Features
SDRAM CAS Latency Time
SDRAM Cycle Time Tras/Trc
SDRAM RAS-to-CAS Delay
SDRAM RAS Precharge Time
System BIOS Cacheable
Video BIOS Cacheable
Memory Hole At 15M-16M
CPU Latency Timer
Delayed Transaction
On-Chip Video Window Size
Use VGA BIOS in VBU Block
3
6/8
3
3
Disabled
Disabled
Disabled
Disabled
Enabled
64MB
Enabled
Item Help
Menu Level
!
!"#$
: Move Enter: Select F5 : Previous Values +/-/PU/PD: Value F10: Save
F6 : Fail-safe defaults Esc:Exit F1: General Help F7 : Optimized Defaults
3-9
