ERM HR C6000, Руководство пользователя

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After the 30ms synchronization time slot is established, if the next time slot needs to be sent, write
framing is required in t2 (including 196bit rate 1 data stream, 144bit rate 3/4 data stream, 96bit rate
1/2 data stream, 96bit Custom control information frame, 80bit data frame header or CSBK data
frame, 72bit voice frame header, end of frame data, data format and content requirements are
designed according to DMR protocol standard. When receiving Rdy_lst_inter interrupt, set the
value of register 0x41. To determine whether the next time slot is sent 0x80 (send), 0x00 (not sent);
if the Rdy_lst_inter interrupt is masked, the 0x41 register can be directly configured in the 30ms
interrupt (TIMER_SLOT_INTER, position 1 in the figure), that is, the configuration is sent and not
sent first. For data writing, this requires the user to ensure that all data preparations that require
framing are completed within t2.
The chip reads the Bit7 flag of 0x40 at the beginning of the t1 time. If it is 1, the data in the data
buffer will be mapped and sent in t1 time.
The CPU can configure the relevant RF channel for transmission according to the RF_Tx_Inter
interrupt.
2) Active reception (active full duplex)
transmit Receive transmit Receive TIME_SLOT_INTER
T2 T1 t3 Rdy_lst_Inter software preparation data
last time interrupt prompt
Sys_Inter
t1=1.7ms,t2=27ms,t3=4ms
The t1 time is the start time of the chip sending code group frame, t2 is the software preparation
data and the configuration transceiver control command time, and t3 is the interrupt for providing
data to the mcu after the chip parsing data is completed. In addition, the Sys_inter interrupt
indicated by the red arrow indicates that the decoded data stream is ready to be completed in the
layer 2 mode, and the 264 or 288 bit data obtained in the physical layer mode is ready to be
completed.
Figure 5.12 Active full-duplex transceiver interrupt diagram
Active reception occurs at the time of active full-duplex. Active full-duplex means that the call
initiator first sends a request, and the MCU configuration register 0x40 turns on the transmission
enable, and actively establishes a 30ms time slot interrupt. After the synchronization time slot is
established, the MCU configuration register 0x41 allocates the transmission time slot and the
reception time slot of the HR_C6000, thereby realizing full-duplex communication.
Active and active reception, active full duplex by controlling 0x41 TxNxtSlotEn (Bit7) and
RxNxtSlotEn (Bit6). The received synchronization slot does not update the synchronization of the
system.
Reception in this mode is called active reception.
3) Passive reception