ERM HR C6000, Руководство пользователя

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Figure 4.16 Using the V_SPI Interface to Read (Write) Timing
The SCLK supports up to 4MHz clock rate.
The frame format of V_SPI is shown below. What needs to be explained is:
The V_SPI interface can only perform one operation at a time, read or write.
When performing a read operation, Cmd=0x83, Addr=0x00, and read 27 individual Data(byte).
When writing, Cmd=0x03, Addr=0x00, and write 27 individual Data(byte).
OMISSIS
Cmd Addr Data0 Data1… Datan
Figure 4.17 V_SPI frame format
To communicate with the Hongrui HR_V3000 vocoder via the V_SPI interface HR_C6000, simply
configure the HR_C6000 register reg0x06 to 0x24. The connection diagram of HR_V3000 and
HR_C6000 and MCU is shown in the figure.
OMISSIS
Figure 4.18 HR_V3000 vocoder and HR_C6000 connection block diagram
OMISSIS
Figure 4.19 shows the interface timing of I2S.
I2S operates in master mode and needs to configure the I2S_CK_M clock frequency via Register
0x2F, calculated as codec operating frequency / (2* (Register 0x2F value + 1)). The I2S_FS_M
clock frequency is configured by Register 0x32, 0x33 (the configured I2S_FS_M clock frequency
must be 8KHz), calculated as codec operating frequency / (2 * ({Register 0x32 value, 0x33 value}
+1)). At the same time, the I2S_CK_M frequency is >34* I2S_FS_M frequency, and the codec
clock frequency is >=6*I2S_CK_M frequency.
When I2S is operating in Master mode, the I2S_CK_M, I2S_FS_M signals can be turned off via
Register 0x36[6]. When 0x36[6]=0, these two signals are turned on, otherwise the two signals are
turned off.