S1R72105 Technical Manual
54
EPSON
Rev.1.0
Select_WithoutATN_Command (0BH)
Executes selection while SCSI ATN is being negated and continues to execute the command phase.
This command is valid in both disconnected and connected condition. Issuing this command while any other
command is in execution causes a command error.
The CPU issues this command after setting the number of bytes of command in the NON_DMA data-size
register.
The command data is written into FIFO.
The IC operates as follows:
Waits for busfree.
Enters arbitration after detecting busfree.
When it beats arbitration, it asserts XSSEL and ID bit and then goes into the selection phase.
After completing selection, it checks the command phase at the timing when XSREQ is asserted and transfers
command data from FIFO.
After completion, it sets the GOOD bit of the MAININT register.
It causes an interruption.
After that, the IC goes into Initiator mode.
Wait_Select_Command (0CH)
Waits for the selection phase and executes the command phase after selection.
Valid only when it is not connected.
Issuing this command in the connected condition sets SCSIINT2 and CMDER bits and causes an interruption.
Any other command being executed continues execution.
When this command is issued, set STATN(bit5) of the SCSIMODE register and clear it when the command is
terminated.
After issuing the command, the IC operates as follows:
(1) Waits for the selection phase.
(2) When selected, checks XSATN. If it is not asserted, the IC operates as mentioned in (5).
If it is asserted, the IC sets the message-out phase and receives a message.
(3) If the message received is other than
“
Identify
”
, the IC operates as mentioned in (6) (The CPU checks the
message in FIFO and responds to it).
(4) When XSATN remains to be asserted after 1-byte message (
“
Identify
”
) is received, the IC terminates its
operation by setting the SATN bit of the SCSIINT1 register and causes an interruption.
If XSATN is negated,
(5) The command phase is set to receive a command.
The IC distinguishes command groups and determines the number of bytes received automatically.
(6) It sets the GOOD bit of the MAININT register and causes an interruption.
After that, the IC goes into Target mode.
Reselect (0DH)
Executes the re-selection phase.
Valid only when it is not connected.
Issuing this command in the connected condition sets the SCSIINT2 and CMDER bits and causes an
interruption. Any other command being executed continues execution.
The IC operates as follows:
Waits for busfree.
Enters arbitration after detecting busfree.
When it beats arbitration, it asserts the XSSEL, XSIO and ID bits and then goes into the re-selection phase.
After completion, it sets the GOOD bit of the MAININT register.
It causes an interruption.
After that, the IC goes into Target mode.