S1R72105 Technical Manual
18
EPSON
Rev.1.0
7.3.2 EPr Interrupt Status(EPrIntStat) R/W
The factor responsible for endpoint interrupt status can be identified by reading this register. When all factors
of endpoint-by-endpoint interruption (interrupt factors at the main source) shown by each bit are cleared, the
relevant bit is cleared.
Following the reading of this register, the bit (interrupt factor at the main source) is cleared by writing the value
read in the interrupt status register (02h or 03h) corresponding to each bit of the appropriate interrupt status
register.
The appropriate interrupt status register is shown in the IntStatWindow_0 register (02h) or IntStatWindow_1
register (03h) by writing a value to the IntIndex register (08h).
Address
Register Name
Bit Symbol
Description
01h EPrIntStat
7:
Reserved
6:
Reserved
5:
Reserved
4:
Reserved
3: EPcIntStat
Endpoint c Interrupt Status
2: EPbIntStat
Endpoint b Interrupt Status
1: EPaIntStat
Endpoint a Interrupt Status
0: EP0IntSta t
Endpoint 0 Interrupt Status
BIT3 Endpoint c Interrupt Status
This bit becomes HIGH when an interrupt factor related to the USB interface shown in the EPcIntStat register is
present.
BIT2 Endpoint b Interrupt Status
This bit becomes HIGH when an interrupt factor related to the USB interface shown in the EPbIntStat register is
present.
BIT1 Endpoint a Interrupt Status
This bit becomes HIGH when an interrupt factor related to the USB interface shown in the EPaIntStat register is
present.
BIT0 Endpoint 0 Interrupt Status
This bit becomes HIGH when an interrupt factor related to the USB interface shown in the EP0IntStat register is
present.
7.3.3 Interrupt Status Window 0(IntStatWindow_0) R/W
The endpoint interrupt status register appears.
The interrupt status to be displayed changes according to the value set at IntIndex_0 of the IntIndex register
(08h).
For set value of the IntIndex register, refer to section “7.4 Detailed Description of Set Values of IntIndex
Register.”
Address
Register Name
Bit Symbol
Description
02h IntStatWindow_0 7:
IntStatWindow_0[7]
6:
IntStatWindow_0[6]
5:
IntStatWindow_0[5]
4:
IntStatWindow_0[4]
3:
IntStatWindow_0[3]
2:
IntStatWindow_0[2]
1:
IntStatWindow_0[1]
0:
IntStatWindow_0[0]
Interrupt Status Window 0
