S1R72105 Technical Manual
Rev.1.0
EPSON
37
7.3.39 FIFO Control (FIFOCTL) R/W
Used for clearing the SCSI-FIFO data and for checking its status.
Address
Register Name
Bit Symbol
Description
31h FIFOCTL
7:
-
6:
-
5:
-
4:
-
3:
-
2: FCLR
CLEAR FIFO
1: FULL
FIFO FULL
0: EMPTY
FIFO EMPTY
BIT7,6,5,4,3 RESERVED
BIT2 CLEAR FIFO
Setting this bit to HIGH clears data stored in SCSI-FIFO.
The bit returns to LOW automatically after clearing.
BIT1 FULL
When this bit is HIGH it means that SCSI-FIFO is full. In this state, any data written into SCSI-FIFO is ignored.
BIT0 EMPTY
When this bit is HIGH it means that SCSI-FIFO is empty. In this state, any attempt to read data from SCSI-FIFO
results in invalid data read out.
7.3.40 FIFO Data (FIFODATA) R/W
This register allows access to SCSI-FIFO from the CPU.
Address
Register Name
Bit Symbol
Description
32h FIFODATA
7:
FD7
(MSB)
6:
FD6
5:
FD5
4: FD4
SCSI_FIFO data
3:
FD3
2:
FD2
1:
FD1
0:
FD0
(LSB)
7.3.41 Non DMA Transfer Size (NDMASIZ) R/W
This register sets the number of bytes of data transfer in Non-DMA mode. In Read mode, the register allows
to read out the size of data yet to be transferred.
Address
Register Name
Bit Symbol
Description
33h NDMASIZ
7:
NSZ7
(MSB)
6:
NSZ6
5:
NSZ5
4: NSZ4
Non DMA Transfer Size
3:
NSZ3
2:
NSZ2
1:
NSZ1
0:
NSZ0
(LSB)
