S1R72105 Technical Manual
Rev.1.0
EPSON
59
the command is issued first and then determine the number of bytes to be received from the second byte by
checking the message code received.
In Initiator mode
The CPU sets the number of bytes of a message to be sent in the NON-DMA data-size register before issuing
this command.
The CPU writes the message to be transferred into FIFO.
The IC operates as follows:
Asserts XSATN.
At the start of execution, negates XSACK if it is asserted.
Sends data in FIFO after checking the message phase at the timing when XSREQ is asserted.
When FIFO is empty, the REQ-ACK handshake is put on hold until when data is accumulated in FIFO.
Negates XSATN after sending the number of bytes to be transferred.
After completion, it sets the GOOD bit of the MAININT register.
It causes an interruption.
Note: Be sure to set the number of bytes of transfer before writing data into FIFO.
Status_Message (1AH)
Executes the message-in phase after executing the status phase.
Valid only in the connected condition. It can be issued in either Target or Initiator mode.
Issuing this command in the disconnected condition sets the SCSIINT2 and CMDER bits and causes an
interruption.
In Target mode
Writes the status and message to be sent into FIFO and issues this command.
The status and message may be written after issuing the command.
The IC operates as follows:
Sets the status phase, fetches 1-byte status byte from FIFO, and transfers it.
Sets the message-in phase, fetches 1-byte message byte from FIFO and transfers it.
When FIFO is empty, the REQ-ACK handshake is put on hold until data is accumulated in FIFO.
After completion, it sets the GOOD bit of the MAININT register.
It causes an interruption.
In Initiator mode
When this command is issued, 1 byte each of status and message is fetched into FIFO.
The CPU reads 1-byte status byte and then 1-byte message byte from FIFO.
The IC operates as follows:
At the start of execution, negates XSACK if it is asserted.
Enters the status into FIFO after checking the status phase at the timing of assertion of XSREQ.
After receiving the status, it enters the message into FIFO after checking the message-in phase at the timing of
assertion of XSREQ.
After completion, it sets the GOOD bit of the MAININT register.
It causes an interruption.
Note: The message length is fixed at one byte.
