Epson S1C63358, Техническое руководство

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S1C63358 TECHNICAL MANUAL
EPSON
87
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
CKSEL0: Prescaler 0 source clock selection register (FFC1H•D0)
CKSEL1: Prescaler 1 source clock selection register (FFC1H•D1)
Selects the source clock of the prescaler.
When "1" is written: OSC3 clock
When "0" is written: OSC1 clock
Reading: Valid
The source clock for the prescaler is selected from OSC1 or OSC3. When "0" is written to the CKSEL0
register, the OSC1 clock is selected as the input clock for the prescaler 0 (for timer 0) and when "1" is
written, the OSC3 clock is selected.
Same as above, the source clock for prescaler 1 is selected by the CKSEL1 register.
When the event counter mode is selected to timer 0, the setting of the CKSEL0 register becomes invalid.
At initial reset, these registers are set to "0".
PTPS00, PTPS01: Timer 0 prescaler division ratio selection register (FFC2H•D2, D3)
PTPS10, PTPS11: Timer 1 prescaler division ratio selection register (FFC3H•D2, D3)
Selects the division ratio of the prescaler.
Two bits of PTPS00 and PTPS01 are the prescaler division ratio selection register for timer 0, and two bits
of PTPS10 and PTPS11 are for timer 1. The prescaler division ratios that can be set by these registers are
shown in Table 4.11.4.2.
Table 4.11.4.2 Selection of prescaler division ratio
PTPS11
PTPS01
1
1
0
0
PTPS10
PTPS00
1
0
1
0
Prescaler division ratio
Source clock / 256
Source clock / 32
Source clock / 4
Source clock / 1
When the event counter mode is selected to timer 0, the setting of the PTPS00 and PTPS01 becomes
invalid.
At initial reset, these registers are set to "0".
EVCNT: Timer 0 counter mode selection register (FFC0H•D2)
Selects a counter mode for timer 0.
When "1" is written: Event counter mode
When "0" is written: Timer mode
Reading: Valid
The counter mode for timer 0 is selected from either the event counter mode or timer mode. When "1" is
written to the EVCNT register, the event counter mode is selected and when "0" is written, the timer
mode is selected.
At initial reset, this register is set to "0".
MODE16: 8-bit
×
2 or 16-bit
×
1 timer mode selection register (FFC0H•D3)
Selects 8-bit
×
2 channels mode (timer 0 and timer 1) or 16-bit
×
1 channel mode.
When "1" is written: 16-bit
×
1 channel
When "0" is written: 8-bit
×
2 channels (timer 0 and timer 1)
Reading: Valid
When 8-bit
×
2 channels is selected, timer 0 and timer 1 can be used independently.
When 16-bit
×
1 channel is selected, timer 0 and timer 1 are chained together and are used as a 16-bit
programmable timer. The clock is input to timer 0 and interrupts will be generated from timer 1.
At initial reset, this register is set to "0".