Epson S1C63358, Техническое руководство

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S1C63358 TECHNICAL MANUAL
EPSON
71
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)
(3) Input signal selection
The analog signals from the AD0 (P40)–AD3 (P43) terminals are input to the multiplexer, and the
analog input channel for A/D conversion is selected by software. This selection can be done using the
CHS register as shown in Table 4.10.4.3.
Table 4.10.4.3 Selection of analog input channel
Input channel
AD3 (P43)
AD2 (P42)
AD1 (P41)
AD0 (P40)
CHS1
1
1
0
0
CHS0
1
0
1
0
(4) A/D conversion operation
An A/D conversion starts by writing "1" to the ADRUN register (FFD0H•D3). However, when the
supply voltage is 1.6 V or less, the V
C2
mode must be set by writing "1" to the VADSEL register before
starting A/D conversion.
For example, when performing A/D conversion using AD1 as the analog input, write "1" (0, 1) to the
CHS register (CHS1, CHS0). However, it is necessary that the P41 terminal has been set as an analog
input terminal. Then write "1" to the ADRUN register. The A/D converter start converting of the
analog signal input to the AD1 terminal.
The built-in sample/hold circuit starts sampling of the analog input specified from t
AD
after writing.
When the sampling is completed, the held analog input voltage is converted into a 8-bit digital value
in successive-approximation architecture.
The conversion result is loaded into the ADDR (ADDR0–ADDR7) register. ADDR0 is the LSB and
ADDR7 is the MSB.
Note: If the CHS register selects an input channel which is not included in the analog input terminals set
by the PAD register (the PAD register can select several terminals simultaneously), the A/D
conversion does not result in a correct converted value.
Example)
Terminal setting:
PAD3=1, PAD2–PAD0=0 (AD3 terminal is used)
Selection of input channel: CHS1=0, CHS0=0 (AD0 is selected)
In a setting like this, the A/D conversion result will be invalid because the contents of the settings are
not matched.
Figure 4.10.4.1 shows the flow chart for starting an A/D conversion.
Set PAD0–PAD3
Enable A/D input channel
Set CHS1, CHS0
Select A/D input channel
Set ADCLK
Select A/D input clock
Set ADRUN to "1"
Start A/D conversion
Fig. 4.10.4.1 Flowchart for starting A/D conversion