S1C17 CORE MANUAL
Seiko Epson Corporation
6-9
(Rev. 1.2)
6.3.8 Software Interrupts
The S1C17 Core provides the
int imm5
and
intl imm5,imm3
instructions allowing the software to generate
any interrupts. The operand
imm5
specifies a vector number (0–31) in the vector table. In addition to this, the
intl
instruction has the operand
imm3
to specify an interrupt level (0–7) to be set to the IL field in the PSR.
The processor performs the same interrupt handling as that of a hardware interrupt.
6.3.9 Interrupt Masked Period
Address misaligned interrupts, NMIs, debug interrupts, and external maskable interrupts are masked between the
specific instructions listed below and cannot be generated during that period (pending state). When the processor
exits the masked period, the pending interrupt can be accepted.
(1) Between the
ext
instruction and the next instruction
(2) Between a delayed branch (
.d
) instruction and the delayed slot instruction that follows
(3) Between the
retd
instruction and the next instruction (located at the return address)
(4) Between the
reti
or
reti.d
*
1
instruction and the next instruction (located at the return address)
*
2
(5) Between the
int
,
ei
,
di
,
slp
, or
halt
instruction and the next instruction
*
2
(6) Between a conditional jump (
jr*
) instruction and the next instruction when the condition has not been met
*
2
*
1 An interrupt that occurs when the
reti.d
instruction is being executed will be accepted after the delayed slot
instruction that follows and the next instruction (located at the return address) are executed.
|
reti.d
Delayed slot instruction
Interrupt masked state
|
Instruction at return address
Interrupt masked state still continues, so the next instruction will be executed
before interrupts can be generated.
Next instruction
Interrupt mask is released.
*
2 The debug interrupt may occur even in the conditions (4) to (6).
