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EPSON
E0C88832/88862 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)
(2) Port selection
Because serial interface input/output ports SIN,
SOUT, SCLK and SRDY are set as I/O port
terminals P10–P13 at initial reset, "1" must be
written to the serial interface enable register
ESIF in order to set these terminals for serial
interface use.
(3) Setting of transfer mode
Select the clock synchronous mode by writing
the data as indicated below to the two bits of the
mode selection registers SMD0 and SMD1.
Master mode:
SMD0 = "0", SMD1 = "0"
Slave mode:
SMD0 = "1", SMD1 = "0"
(4) Clock source selection
In the master mode, select the synchronous
clock source by writing data to the two bits of
the clock source selection registers SCS0 and
SCS1. (See Table 5.7.4.1.)
This selection is not necessary in the slave
mode.
Since all the registers mentioned in (2)–(4) are
assigned to the same address, it's possible to set
them all with one instruction. The parity enable
register EPR is also assigned to this address,
however, since parity is not necessary in the
clock synchronous mode, parity check will not
take place regardless of how they are set.
(5) Clock source control
When the master mode is selected and pro-
grammable timer for the clock source is se-
lected, set transfer rate on the programmable
timer side. (See "5.10 Programmable Timer".)
When the divided signal of OSC3 oscillation
circuit is selected for the clock source, be sure
that the OSC3 oscillation circuit is turned ON
prior to commencing data transfer. (See "5.3
Oscillation Circuits and Operating Mode".)
SCLK
Data
D0 D1 D2 D3 D4 D5 D6 D7
LSB
MSB
Fig. 5.7.6.1 Transfer data configuration using
clock synchronous mode
Below is a description of initialization when
performing clock synchronous transfer, transmit-
receive control procedures and operations.
With respect to serial interface interrupt, see "5.7.8
Interrupt function".
■
Initialization of serial interface
When performing clock synchronous transfer, the
following initial settings must be made.
(1) Setting of transmitting/receiving disable
To set the serial interface into a status in which
both transmitting and receiving are disabled, "0"
must be written to both the transmit enable
register TXEN and the receive enable register
RXEN. Fix these two registers to a disable status
until data transfer actually begins.
5.7.6 Operation of
clock synchronous transfer
Clock synchronous transfer involves the transfer of
8-bit data by synchronizing it to eight clocks. The
same synchronous clock is used by both the
transmitting and receiving sides.
When the serial interface is used in the master
mode, the clock signal selected using SCS0 and
SCS1 is further divided by 1/16 and employed as
the synchronous clock. This signal is then sent via
the SCLK terminal to the slave side (external serial
I/O device).
When used in the slave mode, the clock input to the
SCLK terminal from the master side (external serial
input/output device) is used as the synchronous
clock.
In the clock synchronous mode, since one clock line
(SCLK) is shared for both transmitting and receiv-
ing, transmitting and receiving cannot be per-
formed simultaneously. (Half duplex only is
possible in clock synchronous mode.)
Transfer data is fixed at 8 bits and both transmitting
and receiving are conducted with the LSB (bit 0)
coming first.
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